mirror of https://github.com/YosysHQ/yosys.git
21 lines
480 B
Plaintext
21 lines
480 B
Plaintext
# https://github.com/YosysHQ/yosys/issues/5910
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read_verilog -sv yosys_latch.sv
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hierarchy -check -top yosys_latch
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proc
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design -save gold
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opt
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select -assert-count 2 t:$adlatch
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select -assert-count 2 t:$dlatch
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simplemap
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opt_clean
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select -assert-count 1 t:$_DLATCH_P_
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select -assert-count 1 t:$_DLATCH_N_
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select -assert-count 1 t:$_DLATCH_PN0_
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select -assert-count 1 t:$_DLATCH_NN0_
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select -assert-count 4 t:*
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design -load gold
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equiv_opt -assert -multiclock simplemap
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design -reset
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