mirror of https://github.com/YosysHQ/yosys.git
20 lines
756 B
Plaintext
20 lines
756 B
Plaintext
read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -run :prove -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v
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async2sync
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miter -equiv -make_assert -flatten gold gate miter
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stat
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 6 t:LUTFF
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select -assert-max 5 t:LUT2
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select -assert-max 4 t:LUT3
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select -assert-max 8 t:LUT4
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select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUTFF %% t:* %D
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