opt: Remove O(n²) opt routines across the codebase for pmux

$pmux have bad runtime behavior with large cases and output
bit widths. On one Google test case synthesis takes 57 hours
with these changes it takes 350s.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>

passes/opt/opt_expr.cc

@@ -1491,9 +1491,12 @@ skip_identity:
 				replace_cell(assign_map, module, cell, "mux_undef", ID::Y, cell->getPort(ID::A));
 				goto next_cell;
 			}
+
+			std::vector<RTLIL::SigBit> cell_b_bits = cell->getPort(ID::B).to_sigbit_vector();
 			for (int i = 0; i < cell->getPort(ID::S).size(); i++) {
-				RTLIL::SigSpec old_b = cell->getPort(ID::B).extract(i*width, width);
-				RTLIL::SigSpec old_s = cell->getPort(ID::S).extract(i, 1);
+				auto start = cell_b_bits.begin() + i * width;
+				RTLIL::SigSpec old_b(std::vector<RTLIL::SigBit>{start, start + width});
+				RTLIL::SigSpec old_s{cell->getPort(ID::S)[i]};
 				if (old_b.is_fully_undef() || old_s.is_fully_undef())
 					continue;
 				new_b.append(old_b);

passes/opt/opt_merge.cc

@@ -112,8 +112,12 @@ struct OptMergeThreadWorker
 		int width = GetSize(sig_b) / s_width;
 
 		hashlib::commutative_hash comm;
-		for (int i = 0; i < s_width; i++)
-			comm.eat(hash_pair(sig_s[i], sig_b.extract(i*width, width)));
+		std::vector<RTLIL::SigBit> sig_b_bits = sig_b.to_sigbit_vector();
+		for (int i = 0; i < s_width; i++){
+			auto start = sig_b_bits.begin() + i*width;
+			SigSpec sig_b_i(std::vector<RTLIL::SigBit>{start, start + width});
+			comm.eat(hash_pair(SigSpec{sig_s[i]}, sig_b_i));
+		}
 
 		return comm.hash_into(h);
 	}

passes/opt/opt_muxtree.cc

@@ -124,8 +124,12 @@ struct OptMuxtreeWorker
 
 		// Analyze port B
 		// In case of $pmux, port B is multiple slices, concatenated, one per bit of port S
+		std::vector<RTLIL::SigBit> sig_b_bits = sig_b.to_sigbit_vector();
 		for (int i = 0; i < GetSize(sig_s); i++) {
-			RTLIL::SigSpec sig = sig_b.extract(i*GetSize(sig_a), GetSize(sig_a));
+			auto start = sig_b_bits.begin() + i * GetSize(sig_a);
+			RTLIL::SigSpec sig(std::vector<RTLIL::SigBit>{
+         		start, start + GetSize(sig_a)
+      		});
 			RTLIL::SigSpec ctrl_sig = assign_map(SigSpec{sig_s[i]});
 			portinfo_t portinfo = used_port_bit(sig, this_mux_idx);
 			portinfo.ctrl_sig = sig2bits(ctrl_sig, false).front();

passes/opt/opt_reduce.cc

@@ -112,9 +112,10 @@ struct OptReduceWorker
 		RTLIL::SigSpec new_sig_b, new_sig_s;
 		dict<RTLIL::SigSpec, std::vector<RTLIL::SigBit>> grouped_b_to_s;
 
-		int port_width = sig_a.size();
+		std::vector<SigBit> sig_b_bits = sig_b.to_sigbit_vector();
 		for (int i = 0; i < sig_s.size(); i++) {
-			RTLIL::SigSpec this_b = sig_b.extract(i*port_width, port_width);
+			auto start = sig_b_bits.begin() + i*sig_a.size();
+			RTLIL::SigSpec this_b(std::vector<RTLIL::SigBit>{start, start + sig_a.size()});
 			if (grouped_b_to_s.count(this_b)) {
 				grouped_b_to_s[this_b].push_back(sig_s[i]);
 			} else {

passes/opt/opt_share.cc

@@ -423,12 +423,15 @@ struct OptSharePass : public Pass {
 				std::vector<std::set<OpMuxConn>> mux_port_conns(mux_port_num);
 				int found = 0;
 
+				std::vector<RTLIL::SigBit> mux_b_bits = mux->getPort(ID::B).to_sigbit_vector();
 				for (int mux_port_id = 0; mux_port_id < mux_port_num; mux_port_id++) {
 					SigSpec mux_insig;
 					if (mux_port_id == mux_port_num - 1) {
 						mux_insig = sigmap(mux->getPort(ID::A));
 					} else {
-						mux_insig = sigmap(mux->getPort(ID::B).extract(mux_port_id * mux_port_size, mux_port_size));
+						auto mux_b_bit_slice = mux_b_bits.begin() + mux_port_id * mux_port_size;
+						SigSpec b_extracted_sigspec(std::vector<RTLIL::SigBit>{mux_b_bit_slice, mux_b_bit_slice + mux_port_size});
+						mux_insig = sigmap(b_extracted_sigspec);
 					}
 
 					for (int mux_port_offset = 0; mux_port_offset < mux_port_size; ++mux_port_offset) {