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fabeaf554b
| Author | SHA1 | Date |
|---|---|---|
Jan Bylicki
|
fabeaf554b | |
Emil J
|
a2aeef6c96 | |
github-actions[bot]
|
3d5b1e0a93 | |
Miodrag Milanović
|
5b2252ffd8 | |
Robert O'Callahan
|
0f770285f3 | |
|
Miodrag Milanovic
|
f8341affe3 | |
Jan Bylicki
|
c87c6a97bc |
4
Makefile
4
Makefile
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|
@ -161,7 +161,7 @@ ifeq ($(OS), Haiku)
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CXXFLAGS += -D_DEFAULT_SOURCE
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endif
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YOSYS_VER := 0.58+132
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YOSYS_VER := 0.58+138
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YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
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YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1)
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YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2)
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@ -366,7 +366,7 @@ CXXFLAGS += -I$(PYBIND11_INCLUDE) -DYOSYS_ENABLE_PYTHON
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CXXFLAGS += $(shell $(PYTHON_CONFIG) --includes) -DYOSYS_ENABLE_PYTHON
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OBJS += $(PY_WRAPPER_FILE).o
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PY_GEN_SCRIPT = pyosys/generator.py
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PY_GEN_SCRIPT = $(YOSYS_SRC)/pyosys/generator.py
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PY_WRAP_INCLUDES := $(shell $(UV_ENV) $(PYTHON_EXECUTABLE) $(PY_GEN_SCRIPT) --print-includes)
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endif # ENABLE_PYOSYS
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@ -117,15 +117,6 @@ struct gate_t
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std::string bit_str;
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};
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bool map_mux4;
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bool map_mux8;
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bool map_mux16;
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bool markgroups;
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pool<std::string> enabled_gates;
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bool cmos_cost;
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struct AbcConfig
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{
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std::string global_tempdir_name;
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@ -146,6 +137,12 @@ struct AbcConfig
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bool show_tempdir = false;
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bool sop_mode = false;
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bool abc_dress = false;
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bool map_mux4 = false;
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bool map_mux8 = false;
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bool map_mux16 = false;
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bool markgroups = false;
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pool<std::string> enabled_gates;
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bool cmos_cost = false;
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};
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struct AbcSigVal {
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@ -1382,7 +1379,7 @@ void emit_global_input_files(const AbcConfig &config)
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fprintf(f, "%d %d.00 1.00\n", i+1, config.lut_costs.at(i));
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fclose(f);
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} else {
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auto &cell_cost = cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost();
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auto &cell_cost = config.cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost();
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std::string buffer = stringf("%s/stdcells.genlib", config.global_tempdir_name.c_str());
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FILE *f = fopen(buffer.c_str(), "wt");
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@ -1392,39 +1389,39 @@ void emit_global_input_files(const AbcConfig &config)
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fprintf(f, "GATE ONE 1 Y=CONST1;\n");
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fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_)));
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fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOT_)));
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if (enabled_gates.count("AND"))
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if (config.enabled_gates.count("AND"))
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fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_AND_)));
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if (enabled_gates.count("NAND"))
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if (config.enabled_gates.count("NAND"))
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fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NAND_)));
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if (enabled_gates.count("OR"))
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if (config.enabled_gates.count("OR"))
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fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_OR_)));
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if (enabled_gates.count("NOR"))
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if (config.enabled_gates.count("NOR"))
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fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOR_)));
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if (enabled_gates.count("XOR"))
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if (config.enabled_gates.count("XOR"))
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fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XOR_)));
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if (enabled_gates.count("XNOR"))
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if (config.enabled_gates.count("XNOR"))
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fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XNOR_)));
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if (enabled_gates.count("ANDNOT"))
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if (config.enabled_gates.count("ANDNOT"))
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fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ANDNOT_)));
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if (enabled_gates.count("ORNOT"))
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if (config.enabled_gates.count("ORNOT"))
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fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ORNOT_)));
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if (enabled_gates.count("AOI3"))
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if (config.enabled_gates.count("AOI3"))
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fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI3_)));
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if (enabled_gates.count("OAI3"))
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if (config.enabled_gates.count("OAI3"))
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fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI3_)));
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if (enabled_gates.count("AOI4"))
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if (config.enabled_gates.count("AOI4"))
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fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI4_)));
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if (enabled_gates.count("OAI4"))
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if (config.enabled_gates.count("OAI4"))
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fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI4_)));
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if (enabled_gates.count("MUX"))
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if (config.enabled_gates.count("MUX"))
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fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_MUX_)));
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if (enabled_gates.count("NMUX"))
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if (config.enabled_gates.count("NMUX"))
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fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_NMUX_)));
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if (map_mux4)
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if (config.map_mux4)
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fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(ID($_MUX_)));
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if (map_mux8)
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if (config.map_mux8)
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fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(ID($_MUX_)));
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if (map_mux16)
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if (config.map_mux16)
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fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_)));
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fclose(f);
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}
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@ -1456,6 +1453,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
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RTLIL::Module *mapped_mod = mapped_design->module(ID(netlist));
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if (mapped_mod == nullptr)
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log_error("ABC output file does not contain a module `netlist'.\n");
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bool markgroups = run_abc.config.markgroups;
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for (auto w : mapped_mod->wires()) {
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RTLIL::Wire *orig_wire = nullptr;
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RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
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@ -1998,9 +1996,9 @@ struct AbcPass : public Pass {
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lut_arg = design->scratchpad_get_string("abc.lut", lut_arg);
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luts_arg = design->scratchpad_get_string("abc.luts", luts_arg);
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config.sop_mode = design->scratchpad_get_bool("abc.sop", false);
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map_mux4 = design->scratchpad_get_bool("abc.mux4", map_mux4);
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map_mux8 = design->scratchpad_get_bool("abc.mux8", map_mux8);
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map_mux16 = design->scratchpad_get_bool("abc.mux16", map_mux16);
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config.map_mux4 = design->scratchpad_get_bool("abc.mux4", false);
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config.map_mux8 = design->scratchpad_get_bool("abc.mux8", false);
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config.map_mux16 = design->scratchpad_get_bool("abc.mux16", false);
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config.abc_dress = design->scratchpad_get_bool("abc.dress", false);
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g_arg = design->scratchpad_get_string("abc.g", g_arg);
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@ -2014,7 +2012,7 @@ struct AbcPass : public Pass {
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config.keepff = design->scratchpad_get_bool("abc.keepff", false);
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config.cleanup = !design->scratchpad_get_bool("abc.nocleanup", false);
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config.show_tempdir = design->scratchpad_get_bool("abc.showtmp", false);
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markgroups = design->scratchpad_get_bool("abc.markgroups", markgroups);
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config.markgroups = design->scratchpad_get_bool("abc.markgroups", false);
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if (config.cleanup)
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config.global_tempdir_name = get_base_tmpdir() + "/";
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@ -2094,15 +2092,15 @@ struct AbcPass : public Pass {
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continue;
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}
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if (arg == "-mux4") {
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map_mux4 = true;
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config.map_mux4 = true;
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continue;
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}
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if (arg == "-mux8") {
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map_mux8 = true;
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config.map_mux8 = true;
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continue;
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}
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if (arg == "-mux16") {
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map_mux16 = true;
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config.map_mux16 = true;
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continue;
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}
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if (arg == "-dress") {
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@ -2143,7 +2141,7 @@ struct AbcPass : public Pass {
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continue;
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}
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if (arg == "-markgroups") {
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markgroups = true;
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config.markgroups = true;
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continue;
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}
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break;
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@ -2236,14 +2234,14 @@ struct AbcPass : public Pass {
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}
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if (g == "cmos2") {
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if (!remove_gates)
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cmos_cost = true;
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config.cmos_cost = true;
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gate_list.push_back("NAND");
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gate_list.push_back("NOR");
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goto ok_alias;
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}
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if (g == "cmos3") {
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if (!remove_gates)
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cmos_cost = true;
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config.cmos_cost = true;
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gate_list.push_back("NAND");
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gate_list.push_back("NOR");
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gate_list.push_back("AOI3");
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@ -2252,7 +2250,7 @@ struct AbcPass : public Pass {
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}
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if (g == "cmos4") {
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if (!remove_gates)
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cmos_cost = true;
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config.cmos_cost = true;
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gate_list.push_back("NAND");
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gate_list.push_back("NOR");
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gate_list.push_back("AOI3");
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@ -2263,7 +2261,7 @@ struct AbcPass : public Pass {
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}
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if (g == "cmos") {
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if (!remove_gates)
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cmos_cost = true;
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config.cmos_cost = true;
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gate_list.push_back("NAND");
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gate_list.push_back("NOR");
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gate_list.push_back("AOI3");
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@ -2322,9 +2320,9 @@ struct AbcPass : public Pass {
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ok_alias:
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for (auto gate : gate_list) {
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if (remove_gates)
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enabled_gates.erase(gate);
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config.enabled_gates.erase(gate);
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else
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enabled_gates.insert(gate);
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config.enabled_gates.insert(gate);
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}
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}
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}
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@ -2334,21 +2332,21 @@ struct AbcPass : public Pass {
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if (!config.constr_file.empty() && (config.liberty_files.empty() && config.genlib_files.empty()))
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log_cmd_error("Got -constr but no -liberty/-genlib!\n");
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if (enabled_gates.empty()) {
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enabled_gates.insert("AND");
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enabled_gates.insert("NAND");
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enabled_gates.insert("OR");
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enabled_gates.insert("NOR");
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enabled_gates.insert("XOR");
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enabled_gates.insert("XNOR");
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enabled_gates.insert("ANDNOT");
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enabled_gates.insert("ORNOT");
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// enabled_gates.insert("AOI3");
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// enabled_gates.insert("OAI3");
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// enabled_gates.insert("AOI4");
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// enabled_gates.insert("OAI4");
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enabled_gates.insert("MUX");
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// enabled_gates.insert("NMUX");
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if (config.enabled_gates.empty()) {
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config.enabled_gates.insert("AND");
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config.enabled_gates.insert("NAND");
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config.enabled_gates.insert("OR");
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config.enabled_gates.insert("NOR");
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config.enabled_gates.insert("XOR");
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config.enabled_gates.insert("XNOR");
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config.enabled_gates.insert("ANDNOT");
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config.enabled_gates.insert("ORNOT");
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// config.enabled_gates.insert("AOI3");
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// config.enabled_gates.insert("OAI3");
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// config.enabled_gates.insert("AOI4");
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// config.enabled_gates.insert("OAI4");
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config.enabled_gates.insert("MUX");
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// config.enabled_gates.insert("NMUX");
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}
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emit_global_input_files(config);
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|
|
|
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|
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@ -19,7 +19,11 @@
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|||
|
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#include "kernel/yosys.h"
|
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#include "kernel/sigtools.h"
|
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#include "backends/rtlil/rtlil_backend.h"
|
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#include "kernel/consteval.h"
|
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#include <cstdio>
|
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#include <mutex>
|
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#include <thread>
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|
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USING_YOSYS_NAMESPACE
|
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PRIVATE_NAMESPACE_BEGIN
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@ -66,9 +70,6 @@ struct ExtractFaWorker
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dict<tuple<SigBit, SigBit>, dict<int, pool<SigBit>>> func2;
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dict<tuple<SigBit, SigBit, SigBit>, dict<int, pool<SigBit>>> func3;
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|
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int count_func2;
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int count_func3;
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struct func2_and_info_t {
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bool inv_a, inv_b, inv_y;
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};
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|
|
@ -77,6 +78,26 @@ struct ExtractFaWorker
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bool inv_a, inv_b, inv_c, inv_y;
|
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};
|
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|
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struct Counters {
|
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int count_func2;
|
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int count_func3;
|
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};
|
||||
|
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struct ThreadData {
|
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size_t start;
|
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size_t end;
|
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Counters counters;
|
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ExtractFaWorker* instance;
|
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std::stringstream log_buffer;
|
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std::vector<RTLIL::IdString> ports = {ID::A, ID::B, ID::C, ID::D};
|
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pool<tuple<SigBit, SigBit>> tl_xorxnor2;
|
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pool<tuple<SigBit, SigBit, SigBit>> tl_xorxnor3;
|
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pool<tuple<tuple<SigBit, SigBit>, int, SigBit>> tl_func_2;
|
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pool<tuple<tuple<SigBit, SigBit, SigBit>,int, SigBit>> tl_func_3;
|
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};
|
||||
|
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std::mutex consteval_mtx;
|
||||
|
||||
dict<int, func2_and_info_t> func2_and_info;
|
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dict<int, func3_maj_info_t> func3_maj_info;
|
||||
|
||||
|
|
@ -153,7 +174,7 @@ struct ExtractFaWorker
|
|||
}
|
||||
}
|
||||
|
||||
void check_partition(SigBit root, pool<SigBit> &leaves)
|
||||
void check_partition(SigBit root, pool<SigBit> &leaves, ThreadData& data)
|
||||
{
|
||||
if (config.enable_ha && GetSize(leaves) == 2)
|
||||
{
|
||||
|
|
@ -163,35 +184,38 @@ struct ExtractFaWorker
|
|||
SigBit B = SigSpec(leaves)[1];
|
||||
|
||||
int func = 0;
|
||||
for (int i = 0; i < 4; i++)
|
||||
{
|
||||
bool a_value = (i & 1) != 0;
|
||||
bool b_value = (i & 2) != 0;
|
||||
std::lock_guard lock(consteval_mtx);
|
||||
for (int i = 0; i < 4; i++)
|
||||
{
|
||||
bool a_value = (i & 1) != 0;
|
||||
bool b_value = (i & 2) != 0;
|
||||
|
||||
ce.push();
|
||||
ce.set(A, a_value ? State::S1 : State::S0);
|
||||
ce.set(B, b_value ? State::S1 : State::S0);
|
||||
ce.push();
|
||||
ce.set(A, a_value ? State::S1 : State::S0);
|
||||
ce.set(B, b_value ? State::S1 : State::S0);
|
||||
SigSpec sig = root;
|
||||
|
||||
SigSpec sig = root;
|
||||
if (!ce.eval(sig)) {
|
||||
ce.pop();
|
||||
return;
|
||||
}
|
||||
|
||||
if (sig == State::S1)
|
||||
func |= 1 << i;
|
||||
|
||||
if (!ce.eval(sig)) {
|
||||
ce.pop();
|
||||
return;
|
||||
}
|
||||
|
||||
if (sig == State::S1)
|
||||
func |= 1 << i;
|
||||
|
||||
ce.pop();
|
||||
}
|
||||
|
||||
// log("%04d %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(root));
|
||||
|
||||
if (func == xor2_func || func == xnor2_func)
|
||||
xorxnor2.insert(tuple<SigBit, SigBit>(A, B));
|
||||
data.tl_xorxnor2.insert(tuple<SigBit, SigBit>(A, B));
|
||||
|
||||
count_func2++;
|
||||
func2[tuple<SigBit, SigBit>(A, B)][func].insert(root);
|
||||
data.counters.count_func2++;
|
||||
data.tl_func_2.insert(
|
||||
tuple<tuple<SigBit, SigBit>, int, SigBit>(tuple<SigBit, SigBit>(A, B), func, root)
|
||||
);
|
||||
}
|
||||
|
||||
if (config.enable_fa && GetSize(leaves) == 3)
|
||||
|
|
@ -203,52 +227,70 @@ struct ExtractFaWorker
|
|||
SigBit C = SigSpec(leaves)[2];
|
||||
|
||||
int func = 0;
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
bool a_value = (i & 1) != 0;
|
||||
bool b_value = (i & 2) != 0;
|
||||
bool c_value = (i & 4) != 0;
|
||||
std::lock_guard lock(consteval_mtx);
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
bool a_value = (i & 1) != 0;
|
||||
bool b_value = (i & 2) != 0;
|
||||
bool c_value = (i & 4) != 0;
|
||||
|
||||
ce.push();
|
||||
ce.set(A, a_value ? State::S1 : State::S0);
|
||||
ce.set(B, b_value ? State::S1 : State::S0);
|
||||
ce.set(C, c_value ? State::S1 : State::S0);
|
||||
ce.push();
|
||||
ce.set(A, a_value ? State::S1 : State::S0);
|
||||
ce.set(B, b_value ? State::S1 : State::S0);
|
||||
ce.set(C, c_value ? State::S1 : State::S0);
|
||||
SigSpec sig = root;
|
||||
|
||||
SigSpec sig = root;
|
||||
if (!ce.eval(sig)) {
|
||||
ce.pop();
|
||||
return;
|
||||
}
|
||||
if (sig == State::S1)
|
||||
func |= 1 << i;
|
||||
|
||||
if (!ce.eval(sig)) {
|
||||
ce.pop();
|
||||
return;
|
||||
}
|
||||
|
||||
if (sig == State::S1)
|
||||
func |= 1 << i;
|
||||
|
||||
ce.pop();
|
||||
}
|
||||
|
||||
// log("%08d %s %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(C), log_signal(root));
|
||||
|
||||
if (func == xor3_func || func == xnor3_func)
|
||||
xorxnor3.insert(tuple<SigBit, SigBit, SigBit>(A, B, C));
|
||||
data.tl_xorxnor3.insert(tuple<SigBit, SigBit, SigBit>(A, B, C));
|
||||
|
||||
count_func3++;
|
||||
func3[tuple<SigBit, SigBit, SigBit>(A, B, C)][func].insert(root);
|
||||
data.counters.count_func3++;
|
||||
data.tl_func_3.insert(
|
||||
tuple<tuple<SigBit, SigBit, SigBit>, int, SigBit>(tuple<SigBit, SigBit, SigBit>(A, B, C), func, root)
|
||||
);
|
||||
}
|
||||
}
|
||||
void partition_log_cache(std::stringstream& stream, int depth, SigBit signal, bool format_depth=false) {
|
||||
std::stringstream buf;
|
||||
RTLIL_BACKEND::dump_sigspec(buf, signal, true);
|
||||
if(format_depth) {
|
||||
// at most, this is going to take in maxdepth spaces + 2 brackets + 2 numbers + space + \0
|
||||
std::vector<char> spacer_buffer;
|
||||
spacer_buffer.resize(config.maxdepth + 6);
|
||||
snprintf(spacer_buffer.data(), config.maxdepth + 6, "%*s[%d] ", config.maxdepth-depth, "", depth);
|
||||
stream << spacer_buffer.data();
|
||||
}
|
||||
|
||||
void find_partitions(SigBit root, pool<SigBit> &leaves, pool<pool<SigBit>> &cache, int maxdepth, int maxbreadth)
|
||||
stream << " " << buf.str();
|
||||
if(format_depth)
|
||||
stream << ":";
|
||||
}
|
||||
|
||||
void find_partitions(SigBit root, pool<SigBit> &leaves, pool<pool<SigBit>> &cache, int maxdepth, int maxbreadth, ThreadData& data)
|
||||
{
|
||||
if (cache.count(leaves))
|
||||
return;
|
||||
|
||||
// log("%*s[%d] %s:", 20-maxdepth, "", maxdepth, log_signal(root));
|
||||
// for (auto bit : leaves)
|
||||
// log(" %s", log_signal(bit));
|
||||
// log("\n");
|
||||
partition_log_cache(data.log_buffer, maxdepth, root, true);
|
||||
for (auto bit : leaves)
|
||||
partition_log_cache(data.log_buffer, maxdepth, bit);
|
||||
data.log_buffer << "\n";
|
||||
|
||||
cache.insert(leaves);
|
||||
check_partition(root, leaves);
|
||||
check_partition(root, leaves, data);
|
||||
|
||||
if (maxdepth == 0)
|
||||
return;
|
||||
|
|
@ -262,7 +304,8 @@ struct ExtractFaWorker
|
|||
pool<SigBit> new_leaves = leaves;
|
||||
|
||||
new_leaves.erase(bit);
|
||||
for (auto port : {ID::A, ID::B, ID::C, ID::D}) {
|
||||
|
||||
for (auto port : data.ports) {
|
||||
if (!cell->hasPort(port))
|
||||
continue;
|
||||
auto bit = sigmap(SigBit(cell->getPort(port)));
|
||||
|
|
@ -274,7 +317,7 @@ struct ExtractFaWorker
|
|||
if (GetSize(new_leaves) > maxbreadth)
|
||||
continue;
|
||||
|
||||
find_partitions(root, new_leaves, cache, maxdepth-1, maxbreadth);
|
||||
find_partitions(root, new_leaves, cache, maxdepth-1, maxbreadth, data);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -290,29 +333,55 @@ struct ExtractFaWorker
|
|||
void run()
|
||||
{
|
||||
log("Extracting full/half adders from %s:\n", log_id(module));
|
||||
const size_t num_threads = std::thread::hardware_concurrency();
|
||||
std::vector<std::thread> threads;
|
||||
std::vector<ThreadData> thread_data(num_threads);
|
||||
|
||||
for (auto it : driver)
|
||||
{
|
||||
if (it.second->type.in(ID($_BUF_), ID($_NOT_)))
|
||||
continue;
|
||||
size_t total_elements = driver.size();
|
||||
size_t thread_elements = total_elements / num_threads;
|
||||
for (size_t i = 0; i < num_threads; ++i) {
|
||||
thread_data[i].start = i * thread_elements;
|
||||
thread_data[i].end = (i == num_threads - 1) ? total_elements : (i + 1) * thread_elements;
|
||||
thread_data[i].instance = this;
|
||||
|
||||
SigBit root = it.first;
|
||||
pool<SigBit> leaves = { root };
|
||||
pool<pool<SigBit>> cache;
|
||||
threads.emplace_back([&data = thread_data[i]]() {
|
||||
auto& driver = data.instance->driver;
|
||||
auto& config = data.instance->config;
|
||||
|
||||
if (config.verbose)
|
||||
log(" checking %s\n", log_signal(it.first));
|
||||
for (size_t i = data.start; i < data.end; ++i) {
|
||||
const auto& it = *driver.element(i);
|
||||
if (it.second->type.in(ID($_BUF_), ID($_NOT_)))
|
||||
continue;
|
||||
|
||||
count_func2 = 0;
|
||||
count_func3 = 0;
|
||||
SigBit root = it.first;
|
||||
pool<SigBit> leaves = { root };
|
||||
pool<pool<SigBit>> cache;
|
||||
|
||||
find_partitions(root, leaves, cache, config.maxdepth, config.maxbreadth);
|
||||
if (config.verbose)
|
||||
log(" checking %s\n", log_signal(it.first));
|
||||
|
||||
if (config.verbose && count_func2 > 0)
|
||||
log(" extracted %d two-input functions\n", count_func2);
|
||||
data.instance->find_partitions(root, leaves, cache, config.maxdepth, config.maxbreadth, data);
|
||||
// log("%s", log_buffer.str().c_str());
|
||||
|
||||
if (config.verbose && count_func3 > 0)
|
||||
log(" extracted %d three-input functions\n", count_func3);
|
||||
if (config.verbose && data.counters.count_func2 > 0)
|
||||
log(" extracted %d two-input functions\n", data.counters.count_func2);
|
||||
|
||||
if (config.verbose && data.counters.count_func3 > 0)
|
||||
log(" extracted %d three-input functions\n", data.counters.count_func3);
|
||||
}
|
||||
});
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < num_threads; ++i) {
|
||||
threads[i].join();
|
||||
for(auto& x3 : thread_data[i].tl_xorxnor3)
|
||||
xorxnor3.insert(x3);
|
||||
for(auto& x2 : thread_data[i].tl_xorxnor2)
|
||||
xorxnor2.insert(x2);
|
||||
for(auto& f3 : thread_data[i].tl_func_3)
|
||||
func3[get<0>(f3)][get<1>(f3)].insert(get<2>(f3));
|
||||
for(auto& f2 : thread_data[i].tl_func_2)
|
||||
func2[get<0>(f2)][get<1>(f2)].insert(get<2>(f2));
|
||||
}
|
||||
|
||||
for (auto &key : xorxnor3)
|
||||
|
|
@ -341,10 +410,13 @@ struct ExtractFaWorker
|
|||
int func = it.first;
|
||||
auto f3i = it.second;
|
||||
|
||||
int xor_cnt, xnor_cnt;
|
||||
xor_cnt = func3.at(key).count(xor3_func);
|
||||
xnor_cnt = func3.at(key).count(xnor3_func);
|
||||
if (func3.at(key).count(func) == 0)
|
||||
continue;
|
||||
|
||||
if (func3.at(key).count(xor3_func) == 0 && func3.at(key).count(xnor3_func) != 0) {
|
||||
if (xor_cnt == 0 && xnor_cnt != 0) {
|
||||
f3i.inv_a = !f3i.inv_a;
|
||||
f3i.inv_b = !f3i.inv_b;
|
||||
f3i.inv_c = !f3i.inv_c;
|
||||
|
|
@ -413,13 +485,13 @@ struct ExtractFaWorker
|
|||
}
|
||||
|
||||
bool invert_y = f3i.inv_a ^ f3i.inv_b ^ f3i.inv_c;
|
||||
if (func3.at(key).count(xor3_func)) {
|
||||
if (xor_cnt) {
|
||||
SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID, Y) : Y;
|
||||
for (auto bit : func3.at(key).at(xor3_func))
|
||||
assign_new_driver(bit, YY);
|
||||
}
|
||||
|
||||
if (func3.at(key).count(xnor3_func)) {
|
||||
if (xnor_cnt) {
|
||||
SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID, Y);
|
||||
for (auto bit : func3.at(key).at(xnor3_func))
|
||||
assign_new_driver(bit, YY);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,26 @@
|
|||
read_verilog <<EOT
|
||||
module simple(I1, I2, O);
|
||||
input wire I1;
|
||||
input wire I2;
|
||||
output wire O;
|
||||
|
||||
assign O = I1 | I2;
|
||||
endmodule
|
||||
EOT
|
||||
abc -g all
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module simple(I1, I2, O);
|
||||
input wire I1;
|
||||
input wire I2;
|
||||
output wire O;
|
||||
|
||||
assign O = I1 | I2;
|
||||
endmodule
|
||||
EOT
|
||||
techmap
|
||||
abc -g AND
|
||||
|
||||
select -assert-count 0 t:$_OR_
|
||||
select -assert-count 1 t:$_AND_
|
||||
Loading…
Reference in New Issue