opt_expr: neater variable names, avoid shadowing

passes/opt/opt_expr.cc

@@ -126,7 +126,6 @@ void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
 	log_debug("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
 			cell->type.c_str(), cell->name.c_str(), info.c_str(),
 			module->name.c_str(), log_signal(Y), log_signal(out_val));
-	// log_cell(cell);
 	assign_map.add(Y, out_val);
 	module->connect(Y, out_val);
 	module->remove(cell);
@@ -492,12 +491,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	}
 
 	std::vector<Cell*> module_cells = module->cells();
-	auto iterator = [&](auto&& replace_cell) {
+	auto visitor = [&](auto&& do_action) {
 		if (sort_fails >= effort) {
-			// log("Running on unsorted")
 			for (auto cell : module_cells)
 				if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type))
-					replace_cell(cell);
+				do_action(cell);
 		} else {
 			TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
 			dict<RTLIL::SigBit, Cell*> outbit_to_cell;
@@ -521,7 +519,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 					cells.edge(cells.node(outbit_to_cell.at(bit)), r_index);
 			}
 
-			if (sort_fails < effort && !cells.sort()) {
+			if (!cells.sort()) {
 				// There might be a combinational loop, or there might be constants on the output of cells. 'check' may find out more.
 				// ...unless this is a coarse-grained cell loop, but not a bit loop, in which case it won't, and all is good.
 				log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", log_id(module));
@@ -531,11 +529,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						effort, log_id(module));
 			}
 			for (auto cell : cells.sorted) {
-				replace_cell(cell);
+				do_action(cell);
 			}
 		}
 	};
-	iterator([&](auto& cell)
+	visitor([&](auto& cell)
 	{
 #define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
 #define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_))