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2100 Commits

Author SHA1 Message Date
Sean Luchen 307db1ec50 Add tests for #4976. 2025-04-03 10:01:34 -07:00
Sean Luchen bdcbbf2db6 Fix existing tests/liberty tests, and add them to Makefile. 2025-04-03 09:56:24 -07:00
George Rennie 63b3ce0c77
Merge pull request #4971 from Anhijkt/pow-optimization 
opt_expr: optimize pow of 2 cells
 2025-04-03 14:34:36 +02:00
Jannis Harder 0f13b55173 Liberty file caching with new `libcache` command 
This adds optional in-memory caching of parsed liberty files to speed up
flows that repeatedly parse the same liberty files. To avoid increasing
the memory overhead by default, the caching is disabled by default. The
caching can be controlled globally or on a per path basis using the new
`libcache` command, which also allows purging cached data.
 2025-04-03 13:39:35 +02:00
Anhijkt c57cbfa8f9 opt_expr: add test 2025-04-01 21:54:46 +03:00
Emil J 3a1255546a
Merge pull request #4975 from YosysHQ/emil/opt_expr-cover-with-tests 
opt_expr: expand test coverage
 2025-03-31 20:13:16 +02:00
Emil J. Tywoniak 6194eb939d opt_expr: expand test coverage 2025-03-31 19:31:53 +02:00
Emil J 1b25e1cee0
Merge pull request #4942 from Anhijkt/fix-ice40dsp 
ice40_dsp: fix log_assert issue
 2025-03-28 13:32:17 +01:00
Emil J b2816b22c5
Merge pull request #4965 from YosysHQ/krys/gen_err_files 
More *.err files in test failures
 2025-03-28 13:08:44 +01:00
Emil J ec8b745929
Merge pull request #4733 from antmicro/fix-setundef-pass-for-params 
Fix setting bits of parameters in setundef pass
 2025-03-28 13:06:04 +01:00
Kelvin Chung a0dabf9203 Add extra test 2025-03-26 22:24:41 +00:00
KrystalDelusion 5b6b3d01bf
Update gen-tests-makefile.sh 
Keep file extensions so that e.g. tribuf.ys and tribuf.sh don't try to output to the same log file.
 2025-03-27 10:33:51 +13:00
KrystalDelusion 8a68ae6023
Update gen-tests-makefile.sh 2025-03-27 10:10:49 +13:00
Anhijkt cb03a1ec21 ice40_dsp: fix test 2025-03-26 15:13:05 +02:00
Kelvin Chung 7bbdf6049a Move implementation to constmap and add test 2025-03-26 11:52:55 +00:00
Scott Ashcroft 518986d45c Make cxxrtl tests work on 32-bit by using __builtin_clzll when needed 2025-03-25 13:12:04 +00:00
Krystine Sherwin 0a1c664f02
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY 
Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error.
Add bug4785.ys to tests/verilog to demonstrate.
 2025-03-25 12:15:54 +13:00
KrystalDelusion a647731812
Merge pull request #4677 from YosysHQ/emil/opt_merge-hashing 
opt_merge: hashing performance and correctness
 2025-03-25 10:36:02 +13:00
Emil J. Tywoniak 980a0a15c1 stat: allow gzipped liberty files 2025-03-19 13:43:44 +01:00
Anhijkt 5ae32efca5 ice40_dsp: add test 2025-03-15 20:05:57 +02:00
KrystalDelusion 9f1271bee0
Merge pull request #4922 from Anhijkt/fix-splitcells-assert 
splitcells: Fix the assertion bug caused by out-of-bound offset
 2025-03-14 16:52:38 +13:00
Krystine Sherwin 8405b3b723
select: Fix -none and -clear 
If the selection stack only has one element (which it normally does), then
`design->pop_selection()` automatically resets to the default full selection.
This is a problem for `select [-none | -clear]` which were trying to replace the
current selection, but because the pop added an extra element when the `execute`
returned, the extra selection (the one we actually wanted) gets popped too. So
instead, reassign `design->selection()` in the same way as if we called `select
[selection]`.

Also adds selection stack tests, and removes the accidentally-committed
`boxes_dummy.ys`.
 2025-03-14 16:32:18 +13:00
Krystine Sherwin 9a9cd05f6c
tests: Fixes for boxes 
cxxrtl `test_unconnected_output` and simple_abc9 `abc9.v` both expect boxed modules in the outputs, so make sure they work as expected.
 2025-03-14 14:08:15 +13:00
Krystine Sherwin 061c234559
tests/select: Add tests for selections with boxes 2025-03-14 14:05:40 +13:00
Martin Povišer 6da543a61a
Merge pull request #4818 from povik/macc_v2 
Add `$macc_v2`
 2025-03-12 22:55:40 +01:00
Anhijkt be3dfdc5ad splitcells: add tests 2025-03-10 19:41:22 +02:00
Martin Povišer d8a4991289
Merge pull request #4931 from povik/buf-clean 
opt_clean, simplemap: Add `$buf` handling
 2025-03-10 15:10:17 +01:00
Emil J. Tywoniak 33bfc9d19c opt_merge: test more kinds of cells 2025-03-10 13:14:06 +01:00
Emil J. Tywoniak ae7a97cc2d opt_merge: test some unary cells 2025-03-10 13:14:06 +01:00
Emil J. Tywoniak 176faae7c9 opt_merge: fix trivial binary regression 2025-03-10 13:14:06 +01:00
Martin Povišer 557047fe1e opt_clean, simplemap: Add `$buf` handling 2025-03-07 16:08:38 +01:00
N. Engelhardt 268a034b21
Merge pull request #4866 from YosysHQ/ql_ioff 
add IOFF inference for qlf_k6n10f
 2025-03-03 14:12:09 +00:00
Emil J b4a169527d
Merge pull request #4894 from YosysHQ/emil/abstract 
Add `abstract` pass for formal verification
 2025-02-25 11:16:37 +01:00
Emil J. Tywoniak 3f60a2cc67 abstract: test -slice from:to for -init 2025-02-25 00:22:14 +01:00
Emil J. Tywoniak 3cb7054e53 abstract: test -slice for all modes, -rtlilslice for -init 2025-02-25 00:18:16 +01:00
Emil J. Tywoniak 5bd18613bb abstract: test -init 2025-02-19 23:03:43 +01:00
Emil J. Tywoniak 34e3fcbb31 abstract: test -value 2025-02-18 17:08:45 +01:00
Emil J. Tywoniak d3a90021ad abstract: test -state 2025-02-18 17:08:45 +01:00
Jannis Harder 7cd822b7f5 rtlil: Add {from,to}_hdl_index methods to Wire 
In the past we had the occasional bug due to some place not handling all
4 combinations of upto/downto and zero/nonzero start_offset correctly.
 2025-02-18 17:08:45 +01:00
Emil J. Tywoniak 387d0de383 abstract: -state allow partial abstraction, don't use buffer-normalized mode 2025-02-18 17:08:45 +01:00
Emil J. Tywoniak 6027030215 abstract: -value MVP, use buffer-normalized mode 2025-02-18 17:08:45 +01:00
Emil J. Tywoniak 4637fa74e3 abstract: -init MVP 2025-02-18 17:08:45 +01:00
Emil J. Tywoniak e4ca7b8846 abstract: -state MVP 2025-02-18 17:08:45 +01:00
Krystine Sherwin db5b76edc1
Add test for shifting by INT_MAX 
Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.
 2025-02-14 14:01:27 +13:00
N. Engelhardt 303a386ecc create duplicate IOFFs if multiple output ports are connected to the same register 2025-01-31 11:28:57 +01:00
Jannis Harder 40c690b030 extract_fa: Add test case 2025-01-30 18:45:06 +01:00
N. Engelhardt 9da4fe747e fix bus ioff inference 2025-01-28 11:23:36 +01:00
Martin Povišer 916fe998ab macc_v2: Add test 2025-01-27 13:19:26 +01:00
N. Engelhardt 2241a65f78 fix tests not expecting ioffs 2025-01-24 21:29:10 +01:00
N. Engelhardt 1cf8e7c7db add ioff inference for qlf_k6n10f 2025-01-24 21:17:15 +01:00
Martin Povišer c5fd96ebb0 macc_v2: Start new cell 2025-01-24 12:38:03 +01:00
N. Engelhardt 7e3990b681
Merge pull request #4837 from YosysHQ/json_scopinfo_opt 
write_json: add option to include $scopeinfo cells
 2025-01-10 09:57:22 +00:00
N. Engelhardt 77b28442a5 emit $scopeinfo cells by default 2025-01-08 14:47:46 +01:00
Martin Povišer ca0ace66bc
Merge pull request #4817 from povik/macc_v2-1 
macc: Stop using the B port
 2025-01-08 14:42:51 +01:00
N. Engelhardt dab7905cbe write_json: add option to include $scopeinfo cells 2025-01-08 13:33:56 +01:00
Martin Povišer 652a1b9806 macc: Stop using the B port 
The B port is for single-bit summands. These can just as well be
represented as an additional summand on the A port (which supports
summands of arbitrary width). An upcoming `$macc_v2` cell won't be
special-casing single-bit summands in any way.

In preparation, make the following changes:

 * remove the `bit_ports` field from the `Macc` helper (instead add any
   single-bit summands to `ports` next to other summands)

 * leave `B` empty on cells emitted from `Macc::to_cell`
 2025-01-08 13:03:35 +01:00
Martin Povišer 41e4aa8f0a
Merge pull request #4819 from povik/wreduce-resign 
wreduce: Optimize signedness when possible
 2025-01-06 15:27:55 +01:00
Emil J 6ab5be4a0e
Merge pull request #4814 from YosysHQ/emil/make-test-fasterer 
test: every test everywhere all at once
 2024-12-18 19:02:39 +01:00
Martin Povišer 08778917db wreduce: Optimize signedness when possible 2024-12-16 12:57:08 +01:00
Emil J. Tywoniak 6240aec433 test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
N. Engelhardt 378864d33b bound attributes: handle vhdl null ranges 2024-12-12 11:42:39 +01:00
Emil J. Tywoniak 603e5eb30a test: every test everywhere all at once 2024-12-12 01:28:36 +01:00
N. Engelhardt 03033ab6d4 add more tests for bounds attributes, fix attributes appearing in verilog 2024-12-11 16:11:02 +01:00
Martin Povišer 4bd6061709
Merge pull request #4799 from povik/wrapcell-unused 
wrapcell: Optionally track unused outputs
 2024-12-10 21:16:28 +01:00
Emil J. Tywoniak 55dcf0e200 tests: fix dfflibmap test - false negative conflict multiple -liberty vs enable inference 2024-12-10 15:48:23 +01:00
Martin Povišer 48c8d70a45 wrapcell: Test `check -assert` post wrapping 2024-12-10 15:13:31 +01:00
Emil J 87736a2bf9
Merge pull request #4807 from YosysHQ/emil/dfflibmap-test-dffe 
dfflibmap: cover enable inference with test
 2024-12-10 12:41:11 +01:00
Martin Povišer b0708a38bf
Merge pull request #4678 from povik/tcl-rtlil-api 
Start Tcl design inspection methods
 2024-12-09 15:44:58 +01:00
Emil J. Tywoniak 681b678417 dfflibmap: cover enable inference with test 2024-12-09 14:18:08 +01:00
Miodrag Milanovic 05398889ad Add verific verilog test cases for blackboxes 2024-12-06 16:13:25 +01:00
N. Engelhardt 8b0f665cc5 add setenv pass 2024-12-06 11:25:43 +01:00
Martin Povišer d57d21e566 wrapcell: Optionally track unused outputs 2024-12-05 18:16:53 +01:00
Martin Povišer 59a96470df
Merge pull request #4773 from povik/wrapcell 
wrapcell: Add new command
 2024-12-04 11:49:51 +01:00
Martin Povišer 14ee5ce800
Merge pull request #4787 from povik/booth-macc 
booth: Map simple `$macc` instances too
 2024-12-04 11:49:34 +01:00
Emil J. Tywoniak 6edf9c86cb libparse: add LibertyMergedCells, enable multiple -liberty args for dfflibmap and clockgate 2024-12-03 17:36:00 +01:00
Emil J 52336369fa
Merge pull request #4783 from YosysHQ/emil/blockrom-driver-conflict 
tests: fix blockrom.v driver conflict
 2024-12-03 16:29:43 +01:00
Martin Povišer 109d97bb40
Merge pull request #4706 from povik/keep_hierarchy-adjustalgo 
Adjust `keep_hierarchy` behavior
 2024-12-03 12:18:28 +01:00
Martin Povišer f0704b6ede Redo integer passing on top of bignum 2024-12-02 19:56:51 +01:00
Emil J. Tywoniak c26966e3db tests: fix blockrom.v driver conflict 2024-12-02 16:56:42 +01:00
Emil J. Tywoniak fe64a714a9 techmap: add a Sklansky option for `$lcu` mapping 2024-12-02 11:34:58 +01:00
Martin Povišer 1ded817beb booth: Map simple `$macc` instances too 2024-12-01 16:00:04 +01:00
Emil J. Tywoniak 3ebc714dbc techmap: test consistently with other equiv_make tests 2024-11-29 00:15:02 +01:00
Emil J. Tywoniak 91844968fd techmap: wrap builtin $lcu as golden module in PPA tests 2024-11-29 00:13:21 +01:00
Emil J. Tywoniak a41ef0271c techmap: remove ppa.nomatch by purging internal signals 2024-11-29 00:03:49 +01:00
Emil J. Tywoniak 4bf3677640 techmap: set Han-Carlson adder priority consistent with Kogge-Stone 2024-11-28 23:54:00 +01:00
Emil J. Tywoniak 3f078d9afa tests: rework Kogge-Stone test consistently with Han-Carlson 2024-11-28 15:33:21 +01:00
Emil J. Tywoniak 1a562f9605 techmap: add TCL test for Han-Carlson adder 2024-11-28 15:33:21 +01:00
Emil J. Tywoniak 289673a807 tests: add support for tcl tests 2024-11-28 15:33:21 +01:00
Martin Povišer 79e9258a31 wrapcell: Add new command 2024-11-27 14:01:00 +01:00
Miodrag Milanović 29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific 
verific: fix blackbox regression and add test case
 2024-11-25 15:06:54 +01:00
Emil J 5b6baa3ef1
Merge pull request #4744 from YosysHQ/emil/clockgate-liberty 
clockgate: add -liberty
 2024-11-20 15:04:00 +01:00
George Rennie 9043dc0ad6
tests: replace read_ilang with read_rtlil 
* #4612 was written before read_ilang was deprecated but merged after so caused test failures. This switches read_ilang to read_rtlil
 2024-11-20 14:54:23 +01:00
Emil J cc17d5bb70
Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width 
opt_demorgan: skip zero width cells
 2024-11-20 13:33:16 +01:00
Emil J 18459b4b09
Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width 
opt_reduce: keep at least one input to $reduce_or/and cells
 2024-11-20 13:33:04 +01:00
Martin Povišer 7ebe451f9a
Merge pull request #4714 from georgerennie/george/proc_dff_bug_multiple_sigs 
proc_dff: fix early return bug
 2024-11-20 13:26:32 +01:00
Martin Povišer 270846a49a
Merge pull request #4723 from povik/memv2-nordports 
rtlil: Adjust internal check for `$mem_v2` cells
 2024-11-18 15:44:39 +01:00
Emil J. Tywoniak a5bc36f77e clockgate: add -dont_use 2024-11-18 13:45:30 +01:00
Emil J. Tywoniak b08441d95c clockgate: shuffle test liberty to exercise comparison better 2024-11-18 12:48:50 +01:00
Emil J. Tywoniak 1e3f8cc630 clockgate: add test liberty file 2024-11-18 12:45:27 +01:00
Emil J. Tywoniak c921d85a85 clockgate: fix test comments 2024-11-18 12:33:09 +01:00
Martin Povišer 0d5c412807 read_liberty: s/busses/buses/ 2024-11-12 13:33:41 +01:00
Martin Povišer 56a9202a97 Add read_liberty tests of new options 2024-11-12 13:29:16 +01:00
Martin Povišer 5a0cb5d453 Check in filtered samples of IHP's Liberty data for tests 2024-11-12 13:28:15 +01:00
Martin Povišer 1b1a6c4aed
Merge pull request #4525 from georgerennie/peepopt_clock_gate 
peepopt: Add formal opt to rewrite latches to ffs in clock gates
 2024-11-11 14:49:09 +01:00
mszelwiga 8e508f2a2a Fix setting bits of parameters in setundef pass 
This commit also adds test that verifies correctness of this change.
 2024-11-08 17:03:08 +01:00
Martin Povišer e82e5f8b13 rtlil: Adjust internal check for `$mem_v2` cells 
There's a mismatch between what `kernel/mem.cc` emits for memories
with no read ports and what the internal RTLIL check expects.

The point of dispute it whether some of the parameters relating to read
ports have a zero-width value in this case. The `mem.cc` code says no,
the internal checker says yes.

Surveying the other `$mem_v2` parameters, and internal cell parameters
in general, I am inclined to side with the `mem.cc` code.

This breaks RTLIL compatibility but for an obscure edge case.
 2024-11-08 15:18:43 +01:00
Miodrag Milanovic df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
KrystalDelusion 4343c791cb
Merge pull request #4704 from YosysHQ/krys/drop_ilang 
Remove references to ilang
 2024-11-08 11:28:06 +13:00
George Rennie a31c968340 tests/bufnorm: add test for bufnorm of constant 2024-11-07 12:55:50 +01:00
George Rennie c23e64a236 tests/proc: add proc_dff bug 4712 as testcase 2024-11-07 00:10:17 +01:00
N. Engelhardt 2de9f00368
Merge pull request #4620 from RCoeurjoly/fix-vcd-parsing-ghdl-var-spacing 2024-11-06 16:29:07 +01:00
N. Engelhardt 9068ec5566
Merge pull request #4627 from RCoeurjoly/roland/assume_x 2024-11-06 16:27:30 +01:00
Martin Povišer 69a36aec3b Add keep_hierarchy test 2024-11-05 09:28:45 +01:00
Krystine Sherwin ee73a91f44
Remove references to ilang 2024-11-05 12:36:31 +13:00
Lofty 3250f2b82b
Merge pull request #4700 from povik/select-list-mod 
Add `select -list-mod`
 2024-11-04 15:38:42 +00:00
Martin Povišer d752ca4847 Fix test after option change 2024-11-04 16:26:46 +01:00
Martin Povišer f7400a06cd Fix test 2024-11-04 16:19:59 +01:00
Martin Povišer 23922faecc Test new Tcl methods 2024-11-04 16:18:50 +01:00
Martin Povišer c9ed6d8dcf cellmatch: Rename `-lut_attrs` to `-derive_luts`; document option 2024-11-04 14:28:40 +01:00
Martin Povišer 7aa3fdab80 select: Add `-list-mod` option 2024-11-04 13:16:13 +01:00
Martin Povišer 9432e972f7
Merge pull request #4626 from povik/select-t-at 
select: Add new `t:@<name>` syntax
 2024-10-16 10:18:05 +02:00
Emil J. Tywoniak f9f509bc25 select: add t:@<name> test 2024-10-15 21:06:06 +02:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Miodrag Milanović ecec156965
Merge pull request #4643 from donn/fix_wheels 
wheels: fix missing yosys-abc/share directory
 2024-10-09 18:05:58 +02:00
Emil J 038e262332
Merge pull request #4624 from YosysHQ/emil/cxxrtl-smoke-test 
cxxrtl: test stream operator
 2024-10-09 05:57:13 -07:00
Mohamed Gaber 3d6b8b8e1a
wheels: fix missing yosys-abc/share directory 
* `misc/__init__.py`:
  * checks if there's a `yosys-abc` in the same directory - if yes, sets the variable `sys._pyosys_abc`
  * checks if there's a `share` in the same directory - if yes, sets the variable `sys._pyosys_share_dirname`
* `yosys.cc::init_share_dirname`: check for `sys._pyosys_share_dirname`, use it at the highest priority if Python is enabled
* `yosys.cc::init_abc_executable_name`: check for `sys._pyosys_abc`, use it at at the highest priority if Python is enabled
* `Makefile`: add new target, `share`, to only create the extra targets
* `setup.py`: compile libyosys.so, yosys-abc and share, and copy them all as part of the pyosys build
* `test/arch/ecp5/add_sub.py`: ported `add_sub.ys` to Python to act as a test for the share directory and abc with Python wheels, used in CI
 2024-10-09 13:09:14 +03:00
Martin Povišer e46cc57cc4
Merge pull request #4613 from povik/err-never-silence 
log: Never silence `log_cmd_error`
 2024-10-07 16:12:31 +02:00
Martin Povišer 0aab8b4158
Merge pull request #4605 from povik/liberty-unit-delay 
read_liberty: Optionally import unit delay arcs
 2024-10-07 16:11:51 +02:00
Martin Povišer 74e92d10e8
Merge pull request #4593 from povik/aiger2 
New aiger backend
 2024-10-07 16:11:25 +02:00
Martin Povišer 6c1450fdaf
Merge pull request #4607 from povik/ql-nodiv 
quicklogic: Avoid carry chains in division mapping
 2024-10-07 16:11:11 +02:00
Martin Povišer ca5c2fdff1 quicklogic: Relax the LUT number test 2024-10-07 15:27:03 +02:00
Martin Povišer b01b17689e Add test of error not getting silenced 2024-10-07 14:49:17 +02:00
Martin Povišer d0a11e26f3 aiger2: Add test of writing a flattened view 2024-10-07 12:04:33 +02:00
Lofty 13ecbd5c76 quicklogic: test that dividing by a constant does not infer carry chains 2024-10-03 20:05:28 +01:00
Roland Coeurjoly 5ea2c6e6e5 Assume x values for missing signal data in FST 
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-10-02 12:08:48 +02:00
Emil J. Tywoniak 997cb30f1f cxxrtl: test stream operator 2024-10-01 13:25:07 +02:00
Roland Coeurjoly 76c615b2ae Fix: handle VCD variable references with and without whitespace 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-10-01 11:51:20 +02:00
rherveille ce7db661a8
Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00
George Rennie 0572f8806f opt_reduce: add test for constant $reduce_and/or not being zero width 2024-09-25 16:28:41 +01:00
George Rennie e105cae4a9 opt_demorgan: add test for zero width cell 2024-09-25 16:10:16 +01:00
Martin Povišer ea765686b6 aiger2: Adjust hierarchy/port handling 2024-09-18 16:55:02 +02:00
Martin Povišer 6c1fa45995 aiger2: Ingest `$pmux` 2024-09-18 16:42:56 +02:00
Martin Povišer d5756eb9be tests: Add trivial liberty -unit_delay test 2024-09-18 16:17:03 +02:00
Martin Povišer 31476e89b6 tests: Avoid temporary script file 2024-09-18 16:17:03 +02:00
Martin Povišer 8e29675a23 aiger2: Support `$bwmux`, comparison operators 2024-09-17 13:55:58 +02:00
Martin Povišer fb26945a20 Start an 'aiger2' backend 2024-09-17 13:55:58 +02:00
Martin Povišer 4cfdb7ab50 Adjust operation naming in aigmap test 2024-09-17 13:55:58 +02:00
Emil J 52382c6544
Merge pull request #4583 from YosysHQ/emil/clock_gate 
clockgate: centralize clock enables out of FFs
 2024-09-16 15:41:01 +02:00
N. Engelhardt c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
Emil J. Tywoniak 1e999a3cb7 clockgate: EN can be a bit on a multi-bit wire 2024-09-11 19:18:25 +02:00