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781 Commits

Author SHA1 Message Date
Miodrag Milanović 66fca65b58
Merge branch 'master' into mmicko/anlogic 2019-10-18 10:53:56 +02:00
Miodrag Milanović 0b0b0cc0d9
Merge branch 'master' into eddie/pr1352 2019-10-18 10:52:50 +02:00
Miodrag Milanovic 46af9a0ff7 hierarchy - proc reorder 2019-10-18 09:06:43 +02:00
Miodrag Milanovic 0d60902fd9 hierarchy - proc reorder 2019-10-18 09:04:02 +02:00
Miodrag Milanovic e6ad714d20 hierarchy - proc reorder 2019-10-18 08:06:57 +02:00
Miodrag Milanovic 980df499ab Make equivalence work with latest master 2019-10-17 17:24:53 +02:00
Miodrag Milanovic b2f0d75807 remove not needed top module 2019-10-17 17:11:11 +02:00
Miodrag Milanovic 1a399c6456 remove not needed top module 2019-10-17 17:11:11 +02:00
Miodrag Milanovic a198bcdd4f split muxes synth per type 2019-10-17 17:11:11 +02:00
Miodrag Milanovic 36af102801 Test dffs separetely 2019-10-17 17:11:11 +02:00
Miodrag Milanovic 487b38b124 Split latches into separete tests 2019-10-17 17:11:11 +02:00
Miodrag Milanovic fba6229718 Fix formatting 2019-10-17 17:10:42 +02:00
Miodrag Milanovic 53bc499a90 Clean verilog code from not used define block 2019-10-17 17:10:42 +02:00
Miodrag Milanovic d37cd267a5 Removed alu and div_mod test as agreed, ignore generated files 2019-10-17 17:10:42 +02:00
Miodrag Milanovic a7fbc8c3fe Test per flip-flop type 2019-10-17 17:10:42 +02:00
Eddie Hung 3b44084320 Add -assert 2019-10-17 17:10:42 +02:00
Eddie Hung 8422ad3e3a Use built-in async2sync call as per #1417 2019-10-17 17:10:42 +02:00
Eddie Hung 5b7bc3ab85 Update mul test to DSP48E1 2019-10-17 17:10:02 +02:00
Eddie Hung 08bd1816e3 Update area for div_mod 2019-10-17 17:10:02 +02:00
Eddie Hung a12801843b Add comment for lack of tristate logic pointing to #1225 2019-10-17 17:10:02 +02:00
Eddie Hung eded90b6b4 Move $x to end as 7f0eec8 2019-10-17 17:10:02 +02:00
SergeyDegtyar 305672170b adffs test update (equiv_opt -multiclock) 2019-10-17 17:10:02 +02:00
Sergey bb70eb977d Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey 68f9239c57 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey df6d0b95da Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey c340d54657 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey 205f52ffe5 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey df7fe40529 Fix div_mod test 2019-10-17 17:10:02 +02:00
SergeyDegtyar 7bc8f0c2e2 Add comment with expected behavior for latches,tribuf tests;Update adffs test 2019-10-17 17:10:02 +02:00
SergeyDegtyar 489444bcba Fix latches.ys test 2019-10-17 17:10:02 +02:00
SergeyDegtyar 6331fa5b02 Remove xilinx_ug901 tests (will be moved to yosys-tests) 2019-10-17 17:10:02 +02:00
SergeyDegtyar 757c476f62 Add smoke tests to tests/xilinx 2019-10-17 17:10:02 +02:00
SergeyDegtyar ca7a58bcc8 Add comments for unproven cells. 2019-10-17 17:08:38 +02:00
SergeyDegtyar 2ae7dec530 Add tests for Xilinx UG901 examples 2019-10-17 17:08:38 +02:00
Clifford Wolf e84cedfae4 Use "(id)" instead of "id" for types as temporary hack 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-14 05:24:31 +02:00
Eddie Hung 3fb604c75d Revert "Add test that is expecting to fail" 
This reverts commit c28d4b8047.
 2019-10-08 12:41:26 -07:00
Eddie Hung cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427 
Refactor peepopt_dffmux and be sensitive to \init when trimming
 2019-10-08 12:38:29 -07:00
Eddie Hung 4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync 
async2sync to be called by equiv_opt only when -async2sync given
 2019-10-08 10:53:44 -07:00
Eddie Hung 5c68da4150 Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf 2019-10-05 09:27:12 -07:00
Miodrag Milanovic 03a3deec43 Cleanup and formating 2019-10-04 11:09:59 +02:00
Miodrag Milanovic a5844e3ceb split latches into separate checks 2019-10-04 11:08:42 +02:00
Miodrag Milanovic 3238ee7d35 check muxes per type 2019-10-04 11:04:18 +02:00
Miodrag Milanovic 91ad3ab717 check ff's separately 2019-10-04 11:00:49 +02:00
Miodrag Milanovic 3d3479b0af Cleanup top modules and not used defines 2019-10-04 10:57:47 +02:00
Miodrag Milanovic 1435b9bf97 remove alu test 2019-10-04 10:55:13 +02:00
Miodrag Milanovic b932654964 Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosys into mmicko/anlogic 2019-10-04 10:52:16 +02:00
Miodrag Milanovic 7785f23719 Check latches type one by one 2019-10-04 10:31:51 +02:00
Miodrag Milanovic 3358b2f185 Removed top module where not needed 2019-10-04 09:53:54 +02:00
Miodrag Milanovic 3c40c81030 Test muxes synth one by one 2019-10-04 08:52:54 +02:00
Miodrag Milanovic d6ef9b1a6b Cleaned verilog code from not used defines 2019-10-04 08:45:58 +02:00