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Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873

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Signed-off-by: Clifford Wolf <[email protected]>
This commit is contained in:
Clifford Wolf
2019-03-19 20:30:28 +01:00
parent a7ac8393d4
commit fe1fb1336b
1 changed files with 4 additions and 2 deletions
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techlibs/xilinx/synth_xilinx.cc
+4 -2
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@@ -120,7 +120,8 @@ struct SynthXilinxPass : public Pass
log("\n"); log("\n");
log(" map_cells:\n"); log(" map_cells:\n");
log(" techmap -map +/xilinx/cells_map.v\n"); log(" techmap -map +/xilinx/cells_map.v\n");
log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n");
log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
log(" clean\n"); log(" clean\n");
log("\n"); log("\n");
log(" check:\n"); log(" check:\n");
@@ -274,7 +275,8 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "map_cells")) if (check_label(active, run_from, run_to, "map_cells"))
{ {
Pass::call(design, "techmap -map +/xilinx/cells_map.v"); Pass::call(design, "techmap -map +/xilinx/cells_map.v");
Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
Pass::call(design, "clean"); Pass::call(design, "clean");
} }