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Rename csa_tree to arith_tree.

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This commit is contained in:
nella
2026-04-13 12:48:05 +02:00
committed by nella
parent c3c577f333
commit fc71719e6e
12 changed files with 90 additions and 90 deletions
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tests/arith_tree/arith_tree_negative.ys
+77
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read_verilog <<EOT
module add2(
input [7:0] a, b,
output [7:0] y
);
assign y = a + b;
endmodule
EOT
hierarchy -auto-top
proc
arith_tree
select -assert-none t:$fa
select -assert-count 1 t:$add
design -reset
read_verilog <<EOT
module add_fanout(
input [7:0] a, b, c,
output [7:0] mid, y
);
wire [7:0] ab = a + b;
assign mid = ab;
assign y = ab + c;
endmodule
EOT
hierarchy -auto-top
proc
arith_tree
select -assert-none t:$fa
design -reset
read_verilog <<EOT
module sub2(
input [7:0] a, b,
output [7:0] y
);
assign y = a - b;
endmodule
EOT
hierarchy -auto-top
proc
arith_tree
select -assert-none t:$fa
select -assert-count 1 t:$sub
design -reset
read_verilog <<EOT
module add_multi_const(
input [7:0] x,
output [7:0] y
);
assign y = 8'd1 + 8'd2 + 8'd3 + x;
endmodule
EOT
hierarchy -auto-top
proc
arith_tree
select -assert-none t:$fa
select -assert-max 1 t:$add
design -reset
read_verilog <<EOT
module add_partial(
input [7:0] a, b, c, d, e,
output [7:0] mid, y
);
wire [7:0] ab = a + b;
assign mid = ab;
assign y = ab + c + d + e;
endmodule
EOT
hierarchy -auto-top
proc
arith_tree
select -assert-count 2 t:$fa
select -assert-count 2 t:$add
design -reset