Cleanup tests

tests/various/bug1480.ys

@@ -1,18 +0,0 @@
-read_verilog << EOF
-module top(...);
-
-input signed [17:0] A;
-input signed [17:0] B;
-output X;
-output Y;
-
-wire [35:0] P;
-assign P = A * B;
-
-assign X = P[0];
-assign Y = P[35];
-
-endmodule
-EOF
-
-synth_xilinx

tests/various/pmux2shiftx.v

@@ -33,7 +33,7 @@ module pmux2shiftx_test (
 	end
 endmodule
 
-module issue01135(input [7:0] i, output o);
+module issue01135(input [7:0] i, output reg o);
 always @*
 case (i[6:3])
     4: o <= i[0];