Merge branch 'main' into nella/latch-toggle

.github/ISSUE_TEMPLATE/config.yml

@@ -5,4 +5,3 @@ contact_links:
   - name: IRC Channel
     url: https://web.libera.chat/#yosys
     about: "#yosys on irc.libera.chat"
-

.github/ISSUE_TEMPLATE/feature_request.yml

@@ -22,4 +22,3 @@ body:
       description: "A clear and detailed description of the feature."
     validations:
       required: true
-

.github/PULL_REQUEST_TEMPLATE.md

@@ -6,4 +6,4 @@ _Explain how this is achieved._
 
 _Make sure your change comes with tests. If not possible, share how a reviewer might evaluate it._
 
-_These template prompts can be deleted when you're done responding to them._
+_These template prompts can be deleted when you're done responding to them._

.github/actions/setup-build-env/action.yml

@@ -33,21 +33,21 @@ runs:
     # and docs/source/getting_started/installation.rst to match.
     - name: Linux common dependencies
       if: runner.os == 'Linux'
-      uses: awalsh128/cache-apt-pkgs-action@v1.6.0
+      uses: awalsh128/cache-apt-pkgs-action@v1.6.1
       with:
         packages: gawk git make python3
         version: ${{ inputs.runs-on }}-commonys
 
     - name: Linux build dependencies
       if: runner.os == 'Linux' && inputs.get-build-deps == 'true'
-      uses: awalsh128/cache-apt-pkgs-action@v1.6.0
+      uses: awalsh128/cache-apt-pkgs-action@v1.6.1
       with:
         packages: bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev libgtest-dev libgmock-dev
         version: ${{ inputs.runs-on }}-buildys
 
     - name: Linux docs dependencies
       if: runner.os == 'Linux' && inputs.get-docs-deps == 'true'
-      uses: awalsh128/cache-apt-pkgs-action@v1.6.0
+      uses: awalsh128/cache-apt-pkgs-action@v1.6.1
       with:
         packages: graphviz xdot
         version: ${{ inputs.runs-on }}-docsys
@@ -56,7 +56,7 @@ runs:
       if: runner.os == 'macOS'
       shell: bash
       run: |
-        brew bundle
+        brew install bison flex gawk libffi git pkg-config python3 bash googletest tcl-tk llvm
 
     - name: Linux runtime environment
       if: runner.os == 'Linux'
@@ -70,7 +70,7 @@ runs:
       shell: bash
       run: |
         echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
-        echo "$(brew --prefix llvm@20)/bin" >> $GITHUB_PATH
+        echo "$(brew --prefix llvm)/bin" >> $GITHUB_PATH
         echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
         echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
         echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV

.github/actions/setup-iverilog/action.yml

@@ -11,7 +11,7 @@ runs:
   steps:
     - name: iverilog Linux deps
       if: steps.restore-iverilog.outputs.cache-hit != 'true' && runner.os == 'Linux'
-      uses: awalsh128/cache-apt-pkgs-action@v1.6.0
+      uses: awalsh128/cache-apt-pkgs-action@v1.6.1
       with:
         packages: autoconf gperf make gcc g++ bison flex libbz2-dev
         version: ${{ inputs.runs-on }}-iverilog
@@ -40,7 +40,7 @@ runs:
         make -j$procs
         make install
 
-    - uses: actions/cache/restore@v4
+    - uses: actions/cache/restore@v6
       id: restore-iverilog
       with:
         path: .local/
@@ -62,7 +62,7 @@ runs:
       run: |
         iverilog -V
 
-    - uses: actions/cache/save@v4
+    - uses: actions/cache/save@v6
       id: save-iverilog
       if: steps.restore-iverilog.outputs.cache-hit != 'true'
       with:

.github/workflows/codeql.yml

@@ -3,7 +3,7 @@ name: "CodeQL"
 on:
   workflow_dispatch:
   schedule:
-    - cron: '0 3 * * *'
+    - cron: '0 3 * * 6'
 
 jobs:
   analyze:
@@ -11,7 +11,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
     - name: Checkout repository
-      uses: actions/checkout@v5
+      uses: actions/checkout@v7
       with:
         submodules: true
         persist-credentials: false

.github/workflows/extra-builds.yml

@@ -3,8 +3,8 @@ name: Test extra build flows
 on:
   pull_request:
   merge_group:
-  #push:
+  push:
-  #  branches: [ main ]
+    branches: [ main ]
   workflow_dispatch:
 
 jobs:
@@ -15,7 +15,7 @@ jobs:
     steps:
       - id: skip_check
         if: ${{ github.event_name != 'merge_group' }}
-        uses: fkirc/skip-duplicate-actions@v5
+        uses: mmicko/skip-duplicate-actions@master
         with:
           # don't run on documentation changes
           paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
@@ -27,6 +27,8 @@ jobs:
         run: |
           if [ "${{ github.event_name }}" = "merge_group" ]; then
             echo "should_skip=false" >> $GITHUB_OUTPUT
+          elif [ "${{ github.event_name }}" = "push" ]; then
+            should_skip=false
           else
             echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT
           fi
@@ -35,15 +37,25 @@ jobs:
     name: Visual Studio build
     runs-on: windows-latest
     needs: [pre_job]
-    if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true'
+    if: (github.event_name == 'push' || github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true'
     steps:
-      - uses: actions/checkout@v5
+      - uses: actions/checkout@v7
         with:
           submodules: true
           persist-credentials: false
 
       - name: Setup MSVC
-        uses: ilammy/msvc-dev-cmd@v1
+        uses: TheMrMilchmann/setup-msvc-dev@v4
+        with:
+          arch: x64
+
+      - name: ccache
+        uses: hendrikmuhs/ccache-action@v1.2.23
+        with:
+          key: vs-build
+          save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }}
+          restore-keys: |
+            vs-build-
 
       - name: Install flex/bison
         shell: pwsh
@@ -57,8 +69,9 @@ jobs:
       - name: Configure CMake
         run: >
           cmake -S . -B build
-          -A x64
+          -G Ninja
           -DCMAKE_BUILD_TYPE=Release
+          -DYOSYS_COMPILER_LAUNCHER=ccache
 
       - name: Build
         run: >
@@ -66,16 +79,77 @@ jobs:
           --config Release
           --parallel
 
-  wasi-build:
+  mingw-build:
-    name: WASI build
+    name: MINGW64 build
-    needs: pre_job
+    runs-on: windows-latest
-    if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true'
+    needs: [pre_job]
-    runs-on: ubuntu-latest
+    if: (github.event_name == 'push' || github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true'
     steps:
-      - uses: actions/checkout@v5
+      - uses: actions/checkout@v7
         with:
           submodules: true
           persist-credentials: false
+
+      - name: Setup MSYS2 (MINGW64)
+        uses: msys2/setup-msys2@v2
+        with:
+          msystem: MINGW64
+          update: true
+
+          install: >-
+            base-devel
+            bison
+            flex
+            gawk
+            diffutils
+            make
+            mingw-w64-x86_64-toolchain
+            mingw-w64-x86_64-cmake
+            mingw-w64-x86_64-gtest
+            mingw-w64-x86_64-pkgconf
+            mingw-w64-x86_64-python
+            mingw-w64-x86_64-tcl
+            mingw-w64-x86_64-libffi
+            mingw-w64-x86_64-git
+            mingw-w64-x86_64-ccache
+
+      - name: ccache
+        uses: hendrikmuhs/ccache-action@v1.2.23
+        with:
+          key: mingw-build
+          save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }}
+          restore-keys: |
+            mingw-build-
+
+      - name: Build Yosys
+        shell: msys2 {0}
+        run: |
+          set -e
+          procs=$(nproc)
+          rm -rf build
+          cmake -S . -B build -DCMAKE_BUILD_TYPE=Release -DYOSYS_COMPILER_LAUNCHER=ccache
+          cmake --build build -j${procs}
+          ctest --test-dir build/tests/unit --output-on-failure
+
+  wasi-build:
+    name: WASI build
+    needs: pre_job
+    if: (github.event_name == 'push' || github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true'
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v7
+        with:
+          submodules: true
+          persist-credentials: false
+
+      - name: ccache
+        uses: hendrikmuhs/ccache-action@v1.2.23
+        with:
+          key: wasi-build
+          save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }}
+          restore-keys: |
+            wasi-build-
+
       - name: Build
         run: |
           WASI_VER=33
@@ -95,34 +169,15 @@ jobs:
             make install)
 
           export PATH=${WASI_SDK_PATH}/bin:$(pwd)/flex-prefix/bin:${PATH}
-          cmake -B build -DCMAKE_TOOLCHAIN_FILE=${WASI_SDK_PATH}/share/cmake/wasi-sdk-p1.cmake -DCMAKE_BUILD_TYPE=Release .
+          cmake -B build -DCMAKE_TOOLCHAIN_FILE=${WASI_SDK_PATH}/share/cmake/wasi-sdk-p1.cmake -DCMAKE_BUILD_TYPE=Release -DYOSYS_COMPILER_LAUNCHER=ccache .
           cmake --build build -j$(nproc)
 
-  nix-build:
-    name: "Build nix flake"
-    needs: pre_job
-    if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true'
-    runs-on: ${{ matrix.os }}
-    strategy:
-      matrix:
-        os: [ubuntu-latest, macos-latest]
-      fail-fast: false
-    steps:
-      - uses: actions/checkout@v5
-        with:
-          submodules: true
-          persist-credentials: false
-      - uses: cachix/install-nix-action@v31
-        with:
-          install_url: https://releases.nixos.org/nix/nix-2.30.0/install
-      - run: nix build .?submodules=1 -L
-
   extra-builds-result:
     runs-on: ubuntu-latest
     needs:
       - vs-build
+      - mingw-build
       - wasi-build
-      - nix-build
     if: always()
     steps:
       - name: Check results

.github/workflows/nix.yml

@@ -0,0 +1,24 @@
+name: Test nix build
+
+on:
+  workflow_dispatch:
+  schedule:
+    - cron: '0 5 * * 6'
+
+jobs:
+  nix-build:
+    name: "Build nix flake"
+    runs-on: ${{ matrix.os }}
+    strategy:
+      matrix:
+        os: [ubuntu-latest, macos-latest]
+      fail-fast: false
+    steps:
+      - uses: actions/checkout@v7
+        with:
+          submodules: true
+          persist-credentials: false
+      - uses: cachix/install-nix-action@v31
+        with:
+          install_url: https://releases.nixos.org/nix/nix-2.30.0/install
+      - run: nix build -L

.github/workflows/prepare-docs.yml

@@ -18,7 +18,7 @@ jobs:
       docs_export: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }}
     steps:
       - id: skip_check
-        uses: fkirc/skip-duplicate-actions@v5
+        uses: mmicko/skip-duplicate-actions@master
         with:
           paths_ignore: '["**/README.md"]'
           # don't cancel in case we're updating docs
@@ -46,7 +46,7 @@ jobs:
     runs-on: [self-hosted, linux, x64, fast]
     steps:
       - name: Checkout Yosys
-        uses: actions/checkout@v4
+        uses: actions/checkout@v7
         with:
           persist-credentials: false
           submodules: true
@@ -72,7 +72,7 @@ jobs:
           cmake --build build --target docs-prepare -j$procs
 
       - name: Upload artifact
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@v7
         with:
           name: cmd-ref-${{ github.sha }}
           path: |

.github/workflows/source-vendor.yml

@@ -12,7 +12,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout repository with submodules
-        uses: actions/checkout@v5
+        uses: actions/checkout@v7
         with:
           submodules: 'recursive'
           persist-credentials: false

.github/workflows/test-build.yml

@@ -3,8 +3,8 @@ name: Build and run tests
 on:
   pull_request:
   merge_group:
-  #push:
+  push:
-  #  branches: [ main ]
+    branches: [ main ]
   workflow_dispatch:
 
 jobs:
@@ -15,7 +15,7 @@ jobs:
     steps:
       - id: skip_check
         if: ${{ github.event_name != 'merge_group' }}
-        uses: fkirc/skip-duplicate-actions@v5
+        uses: mmicko/skip-duplicate-actions@master
         with:
           # don't run on documentation changes
           paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
@@ -26,7 +26,7 @@ jobs:
       - id: set_output
         run: |
           if [ "${{ github.event_name }}" = "merge_group" ]; then
-            echo "should_skip=false" >> $GITHUB_OUTPUT
+            echo "should_skip=true" >> $GITHUB_OUTPUT
           else
             echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT
           fi
@@ -38,7 +38,7 @@ jobs:
     steps:
       - id: skip_check
         if: ${{ github.event_name != 'merge_group' }}
-        uses: fkirc/skip-duplicate-actions@v5
+        uses: mmicko/skip-duplicate-actions@master
         with:
           # don't run on readme changes
           paths_ignore: '["**/README.md"]'
@@ -49,7 +49,9 @@ jobs:
       - id: set_output
         run: |
           if [ "${{ github.event_name }}" = "merge_group" ]; then
-            echo "should_skip=false" >> $GITHUB_OUTPUT
+            echo "should_skip=true" >> $GITHUB_OUTPUT
+          elif [ "${{ github.event_name }}" = "push" ]; then
+            should_skip=false
           else
             echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT
           fi
@@ -68,7 +70,7 @@ jobs:
       fail-fast: false
     steps:
       - name: Checkout Yosys
-        uses: actions/checkout@v5
+        uses: actions/checkout@v7
         with:
           submodules: true
           persist-credentials: false
@@ -79,11 +81,19 @@ jobs:
           runs-on: ${{ matrix.os }}
           get-build-deps: true
 
+      - name: ccache
+        uses: hendrikmuhs/ccache-action@v1.2.23
+        with:
+          key: test-build-${{ matrix.os }}
+          save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }}
+          restore-keys: |
+            test-build-${{ matrix.os }}-
+
       - name: Build
         shell: bash
         run: |
           rm -rf build
-          cmake -B build . -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ -DCMAKE_BUILD_TYPE=Release
+          cmake -B build . -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ -DCMAKE_BUILD_TYPE=Release -DYOSYS_COMPILER_LAUNCHER=ccache
           cmake --build build -j$procs
           ctest --test-dir build/tests/unit
 
@@ -108,7 +118,7 @@ jobs:
     name: Run tests
     runs-on: ${{ matrix.os }}
     needs: [build-yosys, pre_job]
-    if: needs.pre_job.outputs.should_skip != 'true'
+    if: github.event_name != 'push' && needs.pre_job.outputs.should_skip != 'true'
     env:
       CC: clang
     strategy:
@@ -117,7 +127,7 @@ jobs:
       fail-fast: false
     steps:
       - name: Checkout Yosys
-        uses: actions/checkout@v5
+        uses: actions/checkout@v7
         with:
           persist-credentials: false
 
@@ -158,7 +168,7 @@ jobs:
     name: Run test_cell
     runs-on: ${{ matrix.os }}
     needs: [build-yosys, pre_job]
-    if: needs.pre_job.outputs.should_skip != 'true'
+    if: github.event_name != 'push' && needs.pre_job.outputs.should_skip != 'true'
     env:
       CC: clang
     strategy:
@@ -166,7 +176,7 @@ jobs:
         os: [ubuntu-latest]
     steps:
       - name: Checkout Yosys
-        uses: actions/checkout@v5
+        uses: actions/checkout@v7
         with:
           persist-credentials: false
 
@@ -197,14 +207,14 @@ jobs:
     name: Run docs tests
     runs-on: ${{ matrix.os }}
     needs: [build-yosys, pre_docs_job]
-    if: needs.pre_docs_job.outputs.should_skip != 'true'
+    if: github.event_name != 'push' && needs.pre_job.outputs.should_skip != 'true'
     strategy:
       matrix:
         os: [ubuntu-latest]
       fail-fast: false
     steps:
       - name: Checkout Yosys
-        uses: actions/checkout@v5
+        uses: actions/checkout@v7
         with:
           persist-credentials: false
 
@@ -239,14 +249,14 @@ jobs:
     name: Try build docs
     runs-on: [self-hosted, linux, x64, fast]
     needs: [pre_docs_job]
-    if: ${{ needs.pre_docs_job.outputs.should_skip != 'true' && github.repository_owner == 'YosysHQ' }}
+    if: ${{ github.event_name != 'push' && needs.pre_docs_job.outputs.should_skip != 'true' && github.repository_owner == 'YosysHQ' }}
     strategy:
       matrix:
         docs-target: [html, latexpdf]
       fail-fast: false
     steps:
       - name: Checkout Yosys
-        uses: actions/checkout@v4
+        uses: actions/checkout@v7
         with:
           submodules: true
           persist-credentials: false
@@ -276,7 +286,7 @@ jobs:
           cmake --build build --target docs-${{ matrix.docs-target }} -j$procs
 
       - name: Store docs build artifact
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@v7
         with:
           name: docs-build-${{ matrix.docs-target }}
           path: docs/build/

.github/workflows/test-compile.yml

@@ -3,8 +3,8 @@ name: Compiler testing
 on:
   pull_request:
   merge_group:
-  #push:
+  push:
-  #  branches: [ main ]
+    branches: [ main ]
   workflow_dispatch:
 
 jobs:
@@ -15,7 +15,7 @@ jobs:
     steps:
       - id: skip_check
         if: ${{ github.event_name != 'merge_group' }}
-        uses: fkirc/skip-duplicate-actions@v5
+        uses: mmicko/skip-duplicate-actions@master
         with:
           # don't run on documentation changes
           paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
@@ -27,6 +27,8 @@ jobs:
         run: |
           if [ "${{ github.event_name }}" = "merge_group" ]; then
             echo "should_skip=false" >> $GITHUB_OUTPUT
+          elif [ "${{ github.event_name }}" = "push" ]; then
+            should_skip=false
           else
             echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT
           fi
@@ -34,7 +36,7 @@ jobs:
   test-compile:
     runs-on: ${{ matrix.os }}
     needs: pre_job
-    if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true'
+    if: (github.event_name == 'push' || github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true'
     env:
       CXXFLAGS: ${{ startsWith(matrix.compiler, 'gcc') && '-Wp,-D_GLIBCXX_ASSERTIONS' || ''}}
     strategy:
@@ -43,22 +45,19 @@ jobs:
           - ubuntu-latest
         compiler:
           # oldest supported
-          - 'clang-14'
+          - 'clang-16'
           - 'gcc-11'
           # newest, make sure to update maximum standard step to match
           - 'clang-22'
           - 'gcc-16'
         include:
-          # macOS x86
-          - os: macos-15-intel
-            compiler: 'clang-22'
           # macOS arm
           - os: macos-latest
             compiler: 'clang-22'
       fail-fast: false
     steps:
       - name: Checkout Yosys
-        uses: actions/checkout@v5
+        uses: actions/checkout@v7
         with:
           submodules: true
           persist-credentials: false
@@ -69,11 +68,18 @@ jobs:
           runs-on: ${{ matrix.os }}
           get-build-deps: true
 
+      - name: ccache
+        uses: hendrikmuhs/ccache-action@v1.2.23
+        with:
+          key: test-compile-${{ matrix.os }}-${{ matrix.compiler }}
+          save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }}
+          restore-keys: |
+            test-compile-${{ matrix.os }}-${{ matrix.compiler }}-
+
       - name: Setup Cpp
         uses: aminya/setup-cpp@v1
         with:
           compiler: ${{ matrix.compiler }}
-          gcc: ${{ (matrix.os == 'ubuntu-latest' && matrix.compiler == 'clang-14') && '12' || '' }}
 
       - name: Tool versions
         shell: bash
@@ -81,17 +87,12 @@ jobs:
           $CC --version
           $CXX --version
 
-      - name: Fix clang-14 toolchain
-        if: matrix.os == 'ubuntu-latest' && matrix.compiler == 'clang-14'
-        run: |
-          echo 'CXXFLAGS=--gcc-toolchain=/usr -isystem /usr/include/c++/12 -isystem /usr/include/x86_64-linux-gnu/c++/12' >> $GITHUB_ENV
-
       # minimum standard
       - name: Build C++20
         shell: bash
         run: |
           rm -rf build
-          cmake -B build -DCMAKE_CXX_STANDARD=20 . --fresh
+          cmake -B build -DCMAKE_CXX_STANDARD=20 -DYOSYS_COMPILER_LAUNCHER=ccache . --fresh
           cmake --build build --target yosys -j$procs
 
       # maximum standard, only on newest compilers
@@ -100,7 +101,7 @@ jobs:
         shell: bash
         run: |
           rm -rf build
-          cmake -B build -DCMAKE_CXX_STANDARD=26 . --fresh
+          cmake -B build -DCMAKE_CXX_STANDARD=26 -DYOSYS_COMPILER_LAUNCHER=ccache . --fresh
           cmake --build build --target yosys -j$procs
 
   test-compile-result:

.github/workflows/test-sanitizers.yml

@@ -15,7 +15,7 @@ jobs:
     steps:
       - id: skip_check
         if: ${{ github.event_name != 'merge_group' }}
-        uses: fkirc/skip-duplicate-actions@v5
+        uses: mmicko/skip-duplicate-actions@master
         with:
           # don't run on documentation changes
           paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
@@ -27,38 +27,30 @@ jobs:
         run: |
           if [ "${{ github.event_name }}" = "merge_group" ]; then
             echo "should_skip=false" >> $GITHUB_OUTPUT
+          elif [ "${{ github.event_name }}" = "push" ]; then
+            should_skip=false
           else
             echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT
           fi
 
-  run_san:
+  test-sanitizers:
-    name: Build and run tests
+    runs-on: [self-hosted, linux, x64, fast]
-    runs-on: ${{ matrix.os }}
     needs: pre_job
     if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true'
     env:
       CC: clang
       ASAN_OPTIONS: halt_on_error=1 detect_container_overflow=0
       UBSAN_OPTIONS: halt_on_error=1
-    strategy:
-      matrix:
-        os: [ubuntu-latest, macos-latest]
-        sanitizer: ['undefined,address']
-      fail-fast: false
     steps:
       - name: Checkout Yosys
-        uses: actions/checkout@v5
+        uses: actions/checkout@v7
         with:
           submodules: true
           persist-credentials: false
 
-      - name: Setup environment
+      - name: Runtime environment
-        uses: ./.github/actions/setup-build-env
+        run: |
-        with:
+          echo "procs=$(nproc)" >> $GITHUB_ENV
-          runs-on: ${{ matrix.os }}
-          get-build-deps: true
-          get-test-deps: true
-          get-iverilog: true
 
       - name: Build
         shell: bash
@@ -66,7 +58,8 @@ jobs:
           rm -rf build
           cmake -B build . \
                 -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ \
-                -DCMAKE_BUILD_TYPE=Sanitize -DSANITIZE=${{ matrix.sanitizer }}
+                -DCMAKE_BUILD_TYPE=Sanitize -DSANITIZE='undefined,address' \
+                -DYOSYS_COMPILER_LAUNCHER=ccache
           cmake --build build -j$procs
 
       - name: Log yosys-config output
@@ -87,7 +80,7 @@ jobs:
   test-sanitizers-result:
     runs-on: ubuntu-latest
     needs:
-      - run_san
+      - test-sanitizers
     if: always()
     steps:
       - name: Check results
@@ -98,4 +91,4 @@ jobs:
             echo "Some jobs failed or were cancelled"
             exit 1
           fi
-      - run: echo "All good"
+      - run: echo "All good"

.github/workflows/test-verific-cfg.yml

@@ -9,7 +9,7 @@ jobs:
     runs-on: [self-hosted, linux, x64, fast]
     steps:
       - name: Checkout Yosys
-        uses: actions/checkout@v4
+        uses: actions/checkout@v7
         with:
           persist-credentials: false
           submodules: true

.github/workflows/test-verific.yml

@@ -15,7 +15,7 @@ jobs:
     steps:
       - id: skip_check
         if: ${{ github.event_name != 'merge_group' }}
-        uses: fkirc/skip-duplicate-actions@v5
+        uses: mmicko/skip-duplicate-actions@master
         with:
           # don't run on documentation changes
           paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
@@ -37,7 +37,7 @@ jobs:
     runs-on: [self-hosted, linux, x64, fast]
     steps:
       - name: Checkout Yosys
-        uses: actions/checkout@v4
+        uses: actions/checkout@v7
         with:
           persist-credentials: false
           submodules: true
@@ -70,7 +70,7 @@ jobs:
           cmake --build build --target install
 
       - name: Checkout SBY
-        uses: actions/checkout@v4
+        uses: actions/checkout@v7
         with:
           repository: 'YosysHQ/sby'
           path: 'sby'
@@ -125,7 +125,7 @@ jobs:
     runs-on: [self-hosted, linux, x64, fast]
     steps:
       - name: Checkout Yosys
-        uses: actions/checkout@v4
+        uses: actions/checkout@v7
         with:
           persist-credentials: false
           submodules: true

.github/workflows/wheels.yml

@@ -47,7 +47,7 @@ jobs:
     name: Build Wheels | ${{ matrix.os.name }} | ${{ matrix.os.archs }}
     runs-on: ${{ matrix.os.runner }}
     steps:
-      - uses: actions/checkout@v5
+      - uses: actions/checkout@v7
         with:
           fetch-depth: 0
           submodules: true

.gitmodules

@@ -5,3 +5,18 @@
 [submodule "cxxopts"]
 	path = libs/cxxopts
 	url = https://github.com/jarro2783/cxxopts
+[submodule "fmt"]
+	path = libs/fmt
+	url = https://github.com/fmtlib/fmt
+[submodule "tomlplusplus"]
+	path = libs/tomlplusplus
+	url = https://github.com/marzer/tomlplusplus
+[submodule "boost_regex"]
+	path = libs/boost_regex
+	url = https://github.com/MikePopoloski/regex
+[submodule "slang"]
+	path = libs/slang
+	url = https://github.com/MikePopoloski/slang
+[submodule "sv-elab"]
+	path = frontends/slang/lib
+	url = https://github.com/povik/sv-elab

.pre-commit-config.yaml

@@ -0,0 +1,30 @@
+# To use:
+#
+#     pre-commit run -a
+#
+# Or:
+#
+#     pre-commit install  # (runs every time you commit in git)
+#
+# To update this file:
+#
+#     pre-commit autoupdate
+#
+# See https://github.com/pre-commit/pre-commit
+
+exclude: ^libs/
+
+repos:
+- repo: https://github.com/pre-commit/pre-commit-hooks
+  rev: v6.0.0
+  hooks:
+  - id: check-case-conflict
+  - id: check-executables-have-shebangs
+  - id: check-illegal-windows-names
+  - id: check-yaml
+    args: [--allow-multiple-documents]
+  - id: end-of-file-fixer
+  - id: fix-byte-order-marker
+  - id: mixed-line-ending
+    args: [--fix,lf]
+  - id: trailing-whitespace

CHANGELOG

@@ -11,7 +11,7 @@ Yosys 0.65 .. Yosys 0.66
     - C++ compiler with C++20 support is required.
     - Please be aware that next release will also
       migrate to CMake build system.
- 
+
  * New commands and options
     - Added "lattice_dsp_nexus" pass for Lattice Nexus
       DSP inference.
@@ -78,7 +78,7 @@ Yosys 0.61 .. Yosys 0.62
       cascaded cells into tree of cells to improve timing.
     - Added "-gatesi" option to "write_blif" pass to init gates
       under gates_mode in BLIF format.
-    - Added "-on" and "-off" options to "debug" pass for 
+    - Added "-on" and "-off" options to "debug" pass for
       persistent debug logging.
     - Added "linux_perf" pass to control performance recording.
 
@@ -92,7 +92,7 @@ Yosys 0.60 .. Yosys 0.61
  * New commands and options
     - Added "design_equal" pass to support fuzz-test comparison.
     - Added "lut2bmux" pass to convert $lut to $bmux.
-    - Added "-legalize" option to "read_rtlil" pass to prevent 
+    - Added "-legalize" option to "read_rtlil" pass to prevent
       semantic errors.
 
 Yosys 0.59 .. Yosys 0.60
@@ -196,7 +196,7 @@ Yosys 0.53 .. Yosys 0.54
     - Enable single-bit vector wires in RTLIL.
 
  * Xilinx support
-    - Single-port URAM mapping to support memories 2048 x 144b 
+    - Single-port URAM mapping to support memories 2048 x 144b
 
 Yosys 0.52 .. Yosys 0.53
 --------------------------
@@ -222,7 +222,7 @@ Yosys 0.51 .. Yosys 0.52
 --------------------------
  * New commands and options
     - Added "-pattern-limit" option to "share" pass to limit analysis effort.
-    - Added "libcache" pass to control caching of technology library 
+    - Added "libcache" pass to control caching of technology library
       data parsed from liberty files.
     - Added "read_verilog_file_list" to parse verilog file list.
 
@@ -288,7 +288,7 @@ Yosys 0.47 .. Yosys 0.48
 
  * Gowin support
     - Added "-family" option to "synth_gowin" pass.
-    - Cell definitions split by family. 
+    - Cell definitions split by family.
 
  * Verific support
     - Improved blackbox support.
@@ -315,7 +315,7 @@ Yosys 0.45 .. Yosys 0.46
     - Added new "functional backend" infrastructure with three example
       backends (C++, SMTLIB and Rosette).
     - Added new coarse-grain buffer cell type "$buf" to RTLIL.
-    - Added "-y" command line option to execute a Python script with 
+    - Added "-y" command line option to execute a Python script with
       libyosys available as a built-in module.
     - Added support for casting to type in Verilog frontend.
 
@@ -323,7 +323,7 @@ Yosys 0.45 .. Yosys 0.46
     - Added "clockgate" pass for automatic clock gating cell insertion.
     - Added "bufnorm" experimental pass to convert design into
       buffered-normalized form.
-    - Added experimental "aiger2" and "xaiger2" backends, and an 
+    - Added experimental "aiger2" and "xaiger2" backends, and an
       experimental "abc_new" command
     - Added "-force-detailed-loop-check" option to "check" pass.
     - Added "-unit_delay" option to "read_liberty" pass.
@@ -348,10 +348,10 @@ Yosys 0.43 .. Yosys 0.44
     - Build support for Haiku OS.
 
  * New commands and options
-    - Added "keep_hierarchy" pass to add attribute with 
+    - Added "keep_hierarchy" pass to add attribute with
       same name to modules based on cost.
     - Added options "-noopt","-bloat" and "-check_cost" to
-      "test_cell" pass. 
+      "test_cell" pass.
 
  * New back-ends
     - Added initial PolarFire support. ( synth_microchip )
@@ -365,22 +365,22 @@ Yosys 0.42 .. Yosys 0.43
 
  * Verific support
     - Support building Yosys with various Verific library
-      configurations. Can be built now without YosysHQ 
+      configurations. Can be built now without YosysHQ
       specific patch and extension library.
 
 Yosys 0.41 .. Yosys 0.42
 --------------------------
  * New commands and options
     - Added "box_derive" pass to derive box modules.
-    - Added option "assert-mod-count" to "select" pass. 
+    - Added option "assert-mod-count" to "select" pass.
-    - Added option "-header","-push" and "-pop" to "log" pass. 
+    - Added option "-header","-push" and "-pop" to "log" pass.
  * Intel support
     - Dropped Quartus support in "synth_intel_alm" pass.
 
 Yosys 0.40 .. Yosys 0.41
 --------------------------
  * New commands and options
-    - Added "cellmatch" pass for picking out standard cells automatically. 
+    - Added "cellmatch" pass for picking out standard cells automatically.
 
  * Various
     - Extended the experimental incremental JSON API to allow arbitrary
@@ -394,7 +394,7 @@ Yosys 0.40 .. Yosys 0.41
 Yosys 0.39 .. Yosys 0.40
 --------------------------
  * New commands and options
-    - Added option "-vhdl2019" to "read" and "verific" pass. 
+    - Added option "-vhdl2019" to "read" and "verific" pass.
 
  * Various
     - Major documentation overhaul.
@@ -408,7 +408,7 @@ Yosys 0.39 .. Yosys 0.40
 Yosys 0.38 .. Yosys 0.39
 --------------------------
  * New commands and options
-    - Added option "-extra-map" to "synth" pass. 
+    - Added option "-extra-map" to "synth" pass.
     - Added option "-dont_use" to "dfflibmap" pass.
     - Added option "-href" to "show" command.
     - Added option "-noscopeinfo" to "flatten" pass.
@@ -422,7 +422,7 @@ Yosys 0.38 .. Yosys 0.39
       the hierarchy during flattening.
     - Added sequential area output to "stat -liberty".
     - Added ability to record/replay diagnostics in cxxrtl backend.
- 
+
  * Verific support
     - Added attributes to module instantiation.
 
@@ -469,7 +469,7 @@ Yosys 0.35 .. Yosys 0.36
 
  * QuickLogic support
     - Added "K6N10f" support.
-    - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to 
+    - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to
       "synth_quicklogic" pass.
     - Added "ql_bram_merge" pass to merge 18K BRAM cells into TDP36K.
     - Added "ql_bram_types" pass to change TDP36K depending on configuration.
@@ -564,7 +564,7 @@ Yosys 0.29 .. Yosys 0.30
     - Added remaining primitives blackboxes.
 
  * Various
-    - "show -colorattr" will now color the cells, wires, and 
+    - "show -colorattr" will now color the cells, wires, and
       connection arrows.
     - "show -viewer none" will not execute viewer.
 
@@ -739,7 +739,7 @@ Yosys 0.19 .. Yosys 0.20
       operators were not affected.
 
  * Verific support
-    - Proper import of port ranges into Yosys, may result in reversed 
+    - Proper import of port ranges into Yosys, may result in reversed
       bit-order of top-level ports for some synthesis flows.
 
 Yosys 0.18 .. Yosys 0.19
@@ -833,7 +833,7 @@ Yosys 0.14 .. Yosys 0.15
 
  * SystemVerilog
     - Added support for accessing whole sub-structures in expressions
- 
+
  * New commands and options
     - Added glift command, used to create gate-level information flow tracking
       (GLIFT) models by the "constructive mapping" approach
@@ -848,7 +848,7 @@ Yosys 0.13 .. Yosys 0.14
     - Added $bmux and $demux cells and related optimization patterns.
 
  * New commands and options
-    - Added "bmuxmap" and "dmuxmap" passes 
+    - Added "bmuxmap" and "dmuxmap" passes
     - Added "-fst" option to "sim" pass for writing FST files
     - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
       "-sim-gold" options to "sim" pass for co-simulation
@@ -1802,4 +1802,3 @@ Yosys 0.1.0 .. Yosys 0.2.0
      - Added "design -stash/-copy-from/-copy-to"
      - Added "copy" command
      - Added "splice" command
-

CMakeLists.txt

@@ -39,6 +39,7 @@ set(CMAKE_CXX_SCAN_FOR_MODULES NO)
 set(YOSYS_COMPILER_LAUNCHER "" CACHE STRING "Compiler launcher (ccache, sccache)")
 option(YOSYS_ENABLE_COVERAGE "Enable code coverage" OFF)
 option(YOSYS_ENABLE_PROFILING "Enable instruction profiling" OFF)
+option(YOSYS_ENABLE_FUNCTIONAL_TESTS "Enable running functional tests" OFF)
 
 set(YOSYS_PROGRAM_PREFIX "" CACHE STRING "Name prefix for programs, libraries, and data")
 set(YOSYS_COMPONENTS "everything" CACHE STRING "List of components to build (use pass names)")
@@ -52,6 +53,7 @@ option(YOSYS_WITHOUT_ZLIB "Disable zlib integration" OFF)
 option(YOSYS_WITHOUT_LIBFFI "Disable libffi integration" OFF)
 option(YOSYS_WITHOUT_READLINE "Disable readline integration" OFF)
 option(YOSYS_WITHOUT_EDITLINE "Disable editline integration" OFF)
+option(YOSYS_WITHOUT_SLANG "Disable Slang integration" OFF)
 option(YOSYS_WITHOUT_TCL "Disable Tcl integration" OFF)
 option(YOSYS_WITH_PYTHON "Enable Python integration" OFF)
 
@@ -307,6 +309,7 @@ condition(YOSYS_ENABLE_EDITLINE editline_FOUND AND NOT YOSYS_WITHOUT_EDITLINE AN
 condition(YOSYS_ENABLE_TCL tcl_FOUND AND libtommath_FOUND AND NOT YOSYS_WITHOUT_TCL)
 condition(YOSYS_ENABLE_PYTHON Python3Devel_FOUND AND PyosysEnv_FOUND AND YOSYS_WITH_PYTHON)
 condition(YOSYS_ENABLE_VERIFIC YOSYS_VERIFIC_DIR AND zlib_FOUND)
+condition(YOSYS_ENABLE_SLANG NOT YOSYS_WITHOUT_SLANG)
 
 # Describe dependencies and features
 # CMake 4.0 would let us use proper conditions, but that's too new for now.
@@ -534,8 +537,19 @@ if (NOT YOSYS_BUILD_PYTHON_ONLY)
 
 	add_custom_target(test-vanilla
 		COMMAND make vanilla-test ${makefile_vars}
+			ENABLE_FUNCTIONAL_TESTS=$<IF:$<BOOL:${YOSYS_ENABLE_FUNCTIONAL_TESTS}>,1,0>
 		WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/tests
 		DEPENDS ${makefile_depends}
+		USES_TERMINAL
+		JOB_SERVER_AWARE TRUE
+	)
+
+	add_custom_target(test-functional
+		COMMAND make functional ${makefile_vars}
+			ENABLE_FUNCTIONAL_TESTS=$<IF:$<BOOL:${YOSYS_ENABLE_FUNCTIONAL_TESTS}>,1,0>
+		WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/tests
+		DEPENDS ${makefile_depends}
+		USES_TERMINAL
 		JOB_SERVER_AWARE TRUE
 	)
 

CODEOWNERS

@@ -36,6 +36,7 @@ frontends/ast/                 @widlarizer
 techlibs/intel_alm/            @Ravenslofty
 techlibs/gowin/                @pepijndevos
 techlibs/gatemate/             @pu-cc
+techlibs/fabulous/             fpga.research.group@gmail.com
 
 # pyosys
 pyosys/*                       @donn

README.md

@@ -5,6 +5,9 @@ This is a framework for RTL synthesis tools. It currently has
 extensive Verilog-2005 support and provides a basic set of
 synthesis algorithms for various application domains.
 
+Yosys is using [sv-elab](https://github.com/povik/sv-elab) and [slang](https://github.com/MikePopoloski/slang) libraries to provide comprehensive SystemVerilog support.
+It supports an (informally defined) synthesizable subset of SystemVerilog in version IEEE 1800-2017 or IEEE 1800-2023.
+
 Yosys can be adapted to perform any synthesis job by combining
 the existing passes (algorithms) using synthesis scripts and
 adding additional passes as needed by extending the yosys C++
@@ -67,13 +70,9 @@ on Read the Docs.
 When cloning Yosys, some required libraries are included as git submodules. Make
 sure to call e.g.
 
-	$ git clone --recurse-submodules https://github.com/YosysHQ/yosys.git
-
-or
-
 	$ git clone https://github.com/YosysHQ/yosys.git
 	$ cd yosys
-	$ git submodule update --init --recursive
+	$ git submodule update --init
 
 A C++ compiler with C++20 support is required as well as some standard tools
 such as GNU Flex, GNU Bison (>=3.8), CMake (>=3.28), Make (or other CMake
@@ -303,4 +302,3 @@ DOCS (e.g.)
 This will build/rebuild yosys as necessary before generating the website
 documentation from the yosys help commands.  To build for pdf instead of html,
 use the `docs-latexpdf` target.
-

abc

@@ -1 +1 @@
-Subproject commit 1e85fff18db313b29584dc1ff7c2074d2275a381
+Subproject commit e026ed5380f3bdc3beea2ff9ffc23236fc549d5b

backends/aiger/xaiger.cc

@@ -95,7 +95,7 @@ struct XAigerWriter
 		}
 
 		bit2aig_stack.push_back(bit);
-		
+
 		// NB: Cannot use iterator returned from aig_map.insert()
 		//     since this function is called recursively
 

backends/btor/test_cells.sh

@@ -27,4 +27,3 @@ for fn in test_*.il; do
 done
 
 echo "OK."
-

backends/cxxrtl/runtime/README.txt

@@ -15,4 +15,4 @@ file of the simulation toplevel).
 The interfaces declared in `cxxrtl*.h` (without `capi`) are unstable and may change without notice.
 
 For clarity, all of the files in this directory and its subdirectories have unique names regardless
-of the directory where they are placed.
+of the directory where they are placed.

backends/edif/runtest.py

@@ -118,4 +118,3 @@ os.system("set -x; ./test_gold > test_gold.out")
 os.system("set -x; ./test_gate > test_gate.out")
 
 os.system("set -x; md5sum test_gold.out test_gate.out")
-

backends/functional/smtlib.cc

@@ -187,7 +187,7 @@ struct SmtModule {
 	Functional::IR ir;
 	SmtScope scope;
 	std::string name;
-	
+
 	SmtStruct input_struct;
 	SmtStruct output_struct;
 	SmtStruct state_struct;
@@ -256,7 +256,7 @@ struct SmtModule {
 	}
 
 	void write(std::ostream &out)
-	{    
+	{
 		SExprWriter w(out);
 
 		input_struct.write_definition(w);
@@ -266,7 +266,7 @@ struct SmtModule {
 		w << list("declare-datatypes",
 			list(list("Pair", 2)),
 			list(list("par", list("X", "Y"), list(list("pair", list("first", "X"), list("second", "Y"))))));
-		
+
 		write_eval(w);
 		write_initial(w);
 	}

backends/functional/smtlib_rosette.cc

@@ -304,7 +304,7 @@ struct SmtrModule {
 	}
 
 	void write(std::ostream &out)
-	{    
+	{
 		SExprWriter w(out);
 
 		input_struct.write_definition(w);

backends/functional/test_generic.cc

@@ -46,7 +46,7 @@ struct MemContentsTest {
 		error:
 		printf("FAIL\n");
 		int digits = (data_width + 3) / 4;
-		
+
 		for(auto addr = 0; addr < (1<<addr_width); addr++) {
 			if(addr % 8 == 0) printf("%.8x   ", addr);
 			auto it = reference.find(addr);

backends/simplec/test00_uut.v

@@ -11,4 +11,3 @@ endmodule
 module unit_y(input [31:0] a, b, c, output [31:0] y);
   assign y = a & (b | c);
 endmodule
-

backends/smt2/smtio.py

@@ -226,7 +226,7 @@ class SmtIo:
                 print('timeout option is not supported for mathsat.')
                 sys.exit(1)
 
-        if self.solver in ["boolector", "bitwuzla"]:
+        if self.solver == "boolector":
             if self.noincr:
                 self.popen_vargs = [self.solver, '--smt2'] + self.solver_opts
             else:
@@ -236,6 +236,29 @@ class SmtIo:
                 print('timeout option is not supported for %s.' % self.solver)
                 sys.exit(1)
 
+        if self.solver == "bitwuzla":
+            try:
+                help_text = subprocess.check_output([self.solver, "--help"], text=True)
+            except FileNotFoundError:
+                print("%s SMT Solver '%s' not found in path." % (self.timestamp(), self.solver), flush=True)
+                sys.exit(1)
+            if "--lang" in help_text:
+                self.popen_vargs = [self.solver, '--lang', 'smt2'] + self.solver_opts
+                self.unroll = True
+                if self.timeout != 0:
+                    self.popen_vargs.append('--time-limit')
+                    self.popen_vargs.append('%d000' % self.timeout)
+            else:
+                # Versions before 0.3
+                if self.noincr:
+                    self.popen_vargs = [self.solver, '--smt2'] + self.solver_opts
+                else:
+                    self.popen_vargs = [self.solver, '--smt2', '-i'] + self.solver_opts
+                self.unroll = True
+                if self.timeout != 0:
+                    print('timeout option is not supported for %s.' % self.solver)
+                    sys.exit(1)
+
         if self.solver == "abc":
             if len(self.solver_opts) > 0:
                 self.popen_vargs = ['yosys-abc', '-S', '; '.join(self.solver_opts)]

backends/smt2/test_cells.sh

@@ -52,4 +52,3 @@ echo ""
 echo "  All tests passed."
 echo ""
 exit 0
-

backends/smt2/witness.py

@@ -192,8 +192,10 @@ def aiw2yw(input, mapfile, output, skip_x, present_only):
 
     header_lines = list(itertools.islice(input, 0, 2))
 
-    if len(header_lines) == 2 and header_lines[1][0] in ".bcjf":
+    if len(header_lines) == 2 and header_lines[1][0] in ".bj":
         status = header_lines[0].strip()
+        if header_lines[1][0]=='j':
+            raise click.ClickException(f"{input_name}: justice property in AIGER witness not yet supported")
         if status == "0":
             raise click.ClickException(f"{input_name}: file contains no trace, the AIGER status is unsat")
         elif status == "2":

backends/smt2/ywio.py

@@ -398,13 +398,13 @@ class ReadWitness:
 
     def init_step(self):
         return self.step(0)
-    
+
     def non_init_bits(self):
         if len(self) > 1:
             return len(self.bits[1])
         else:
             return sum([sig.width for sig in self.signals if not sig.init_only])
-    
+
     def first_step(self):
         values = WitnessValues()
         # may have issues when non_init_bits is 0

backends/smv/test_cells.sh

@@ -30,4 +30,3 @@ for fn in test_*.il; do
 done
 
 grep '^-- invariant .* is false' *.out || echo 'All OK.'
-

backends/verilog/verilog_backend.cc

@@ -197,14 +197,22 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
 
 	reg_name = id(chunk.wire->name);
 	if (sig.size() != chunk.wire->width) {
-		if (sig.size() == 1)
+		int idx;
-			reg_name += stringf("[%d]", chunk.wire->start_offset +  chunk.offset);
+		if (chunk.wire->upto)
-		else if (chunk.wire->upto)
+			idx = (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset;
-			reg_name += stringf("[%d:%d]", (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset,
-					(chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset);
 		else
-			reg_name += stringf("[%d:%d]", chunk.wire->start_offset +  chunk.offset + chunk.width - 1,
+			idx = chunk.wire->start_offset + chunk.offset;
-					chunk.wire->start_offset +  chunk.offset);
+
+		if (sig.size() == 1)
+			reg_name += stringf("[%d]", idx);
+		else {
+			int left_idx;
+			if (chunk.wire->upto)
+				left_idx = (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset;
+			else
+				left_idx = chunk.wire->start_offset +  chunk.offset + chunk.width - 1;
+			reg_name += stringf("[%d:%d]", left_idx, idx);
+		}
 	}
 
 	return true;
@@ -456,21 +464,22 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 		if (wire->attributes.count(ID::single_bit_vector))
 			range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset);
 	}
+	std::string sign = wire->is_signed ? " signed" : "";
 	if (wire->port_input && !wire->port_output)
-		f << stringf("%s" "input%s %s;\n", indent, range, id(wire->name));
+		f << stringf("%s" "input%s%s %s;\n", indent, sign, range, id(wire->name));
 	if (!wire->port_input && wire->port_output)
-		f << stringf("%s" "output%s %s;\n", indent, range, id(wire->name));
+		f << stringf("%s" "output%s%s %s;\n", indent, sign, range, id(wire->name));
 	if (wire->port_input && wire->port_output)
-		f << stringf("%s" "inout%s %s;\n", indent, range, id(wire->name));
+		f << stringf("%s" "inout%s%s %s;\n", indent, sign, range, id(wire->name));
 	if (reg_wires.count(wire->name)) {
-		f << stringf("%s" "reg%s %s", indent, range, id(wire->name));
+		f << stringf("%s" "reg%s%s %s", indent, sign, range, id(wire->name));
 		if (wire->attributes.count(ID::init)) {
 			f << stringf(" = ");
 			dump_const(f, wire->attributes.at(ID::init));
 		}
 		f << stringf(";\n");
 	} else
-		f << stringf("%s" "wire%s %s;\n", indent, range, id(wire->name));
+		f << stringf("%s" "wire%s%s %s;\n", indent, sign, range, id(wire->name));
 #endif
 }
 

cmake/YosysAbc.cmake

@@ -42,7 +42,9 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME)
 	list(TRANSFORM all_sources PREPEND abc/)
 
 	# Required to get `-DABC_NAMESPACE` below to work consistently.
-	set_source_files_properties(${all_sources} PROPERTIES LANGUAGE CXX)
+	if(NOT MSVC)
+		set_source_files_properties(${all_sources} PROPERTIES LANGUAGE CXX)
+	endif()
 
 	set(main_source abc/src/base/main/main.c)
 	list(REMOVE_ITEM all_sources ${main_source})
@@ -55,9 +57,10 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME)
 	target_include_directories(${arg_LIBNAME} PRIVATE abc/src)
 	target_compile_definitions(${arg_LIBNAME} PUBLIC
 		WIN32_NO_DLL
-		ABC_NAMESPACE=abc
+		$<$<NOT:$<CXX_COMPILER_ID:MSVC>>:ABC_NAMESPACE=abc>
 		ABC_USE_STDINT_H=1
 		ABC_USE_CUDD=1
+		ABC_NO_HISTORY=1
 		ABC_NO_DYNAMIC_LINKING
 		$<${YOSYS_ENABLE_THREADS}:ABC_USE_PTHREADS>
 		$<${YOSYS_ENABLE_READLINE}:ABC_USE_READLINE>
@@ -66,11 +69,11 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME)
 		$<$<CXX_COMPILER_ID:MSVC>:HAVE_STRUCT_TIMESPEC>
 		ABC_NO_RLIMIT
 	)
-	target_compile_options(${arg_LIBNAME} PRIVATE 
+	target_compile_options(${arg_LIBNAME} PRIVATE
 		$<$<CXX_COMPILER_ID:MSVC>:/wd4576>
 		$<$<CXX_COMPILER_ID:MSVC>:/Zc:strictStrings->
 	)
-	
+
 	target_safe_compile_options(${arg_LIBNAME} PRIVATE
 		-fpermissive
 		-fno-exceptions
@@ -81,6 +84,7 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME)
 		-Wno-deprecated-comma-subscript
 		-Wno-format
 		-Wno-constant-logical-operand
+		-Wno-sizeof-pointer-memaccess
 	)
 	target_link_libraries(${arg_LIBNAME} PUBLIC
 		$<${YOSYS_ENABLE_THREADS}:Threads::Threads>

docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst

@@ -279,9 +279,9 @@ This document was originally published in April 2015:
    in line 13 provides a mini synthesis-script to be used to process this cell.
 
    .. code-block:: c
-      :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled 
+      :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled
-               using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a 
+               using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a
-         -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx`` 
+         -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx``
          set and booted with a custom setup routine written in ARM assembler.
       :name: sieve
 

docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst

@@ -18,7 +18,7 @@ be used to convert Verilog designs with simple assertions to BTOR format.
 Download
 ========
 
-This document was originally published in November 2013: 
+This document was originally published in November 2013:
 :download:`Converting Verilog to BTOR PDF</_downloads/APPNOTE_012_Verilog_to_BTOR.pdf>`
 
 ..

docs/source/appendix/env_vars.rst

@@ -29,4 +29,3 @@ Yosys environment variables
 ``YOSYS_ABORT_ON_LOG_ERROR``
    Can be used for debugging Yosys internals.  Setting it to 1 causes abort() to
    be called when Yosys terminates with an error message.
-

docs/source/appendix/primer.rst

@@ -601,7 +601,7 @@ Let's consider the following BNF (in Bison syntax):
 	:class: width-helper invert-helper
 	:name: fig:Basics_parsetree
 
-	Example parse tree for the Verilog expression 
+	Example parse tree for the Verilog expression
 	:verilog:`assign foo = bar + 42;`
 
 The parser converts the token list to the parse tree in :numref:`Fig. %s
@@ -630,7 +630,7 @@ three-address-code intermediate representation. :cite:p:`Dragonbook`
 	:class: width-helper invert-helper
 	:name: fig:Basics_ast
 
-	Example abstract syntax tree for the Verilog expression 
+	Example abstract syntax tree for the Verilog expression
 	:verilog:`assign foo = bar + 42;`
 
 

docs/source/appendix/rtlil_text.rst

@@ -136,11 +136,11 @@ wires, memories, cells, processes, and connections.
 
     <module>            ::= <attr-stmt>* <module-stmt> <module-body> <module-end-stmt>
     <module-stmt>       ::= module <id> <eol>
-    <module-body>       ::= (<param-stmt> 
+    <module-body>       ::= (<param-stmt>
                          |   <conn-stmt>
-                         |   <wire> 
+                         |   <wire>
-                         |   <memory> 
+                         |   <memory>
-                         |   <cell> 
+                         |   <cell>
                          |   <process>)*
     <param-stmt>        ::= parameter <id> <constant>? <eol>
     <constant>          ::= <value> | <integer> | <string>
@@ -170,9 +170,9 @@ See :ref:`sec:rtlil_sigspec` for an overview of signal specifications.
 
 .. code:: BNF
 
-    <sigspec> ::= <constant> 
+    <sigspec> ::= <constant>
                |  <wire-id>
-               |  <sigspec> [ <integer> (:<integer>)? ] 
+               |  <sigspec> [ <integer> (:<integer>)? ]
                |  { <sigspec>* }
 
 When a ``<wire-id>`` is specified, the wire must have been previously declared.
@@ -202,12 +202,12 @@ See :ref:`sec:rtlil_cell_wire` for an overview of wires.
     <wire>          ::= <attr-stmt>* <wire-stmt>
     <wire-stmt>     ::= wire <wire-option>* <wire-id> <eol>
     <wire-id>       ::= <id>
-    <wire-option>   ::= width <integer> 
+    <wire-option>   ::= width <integer>
-                     |  offset <integer> 
+                     |  offset <integer>
-                     |  input <integer> 
+                     |  input <integer>
-                     |  output <integer> 
+                     |  output <integer>
-                     |  inout <integer> 
+                     |  inout <integer>
-                     |  upto 
+                     |  upto
                      |  signed
 
 Memories
@@ -223,8 +223,8 @@ See :ref:`sec:rtlil_memory` for an overview of memory cells, and
 
     <memory>        ::= <attr-stmt>* <memory-stmt>
     <memory-stmt>   ::= memory <memory-option>* <id> <eol>
-    <memory-option> ::= width <integer> 
+    <memory-option> ::= width <integer>
-                     |  size <integer> 
+                     |  size <integer>
                      |  offset <integer>
 
 Cells
@@ -299,9 +299,9 @@ be:
 .. code:: BNF
 
     <sync>          ::= <sync-stmt> <update-stmt>*
-    <sync-stmt>     ::= sync <sync-type> <sigspec> <eol> 
+    <sync-stmt>     ::= sync <sync-type> <sigspec> <eol>
                      |  sync global <eol>
-                     |  sync init <eol> 
+                     |  sync init <eol>
                      |  sync always <eol>
     <sync-type>     ::= low | high | posedge | negedge | edge
     <update-stmt>   ::= update <dest-sigspec> <src-sigspec> <eol>

docs/source/cell/word_logic.rst

@@ -29,7 +29,7 @@ There are 2 products to be summed, so ``\DEPTH`` shall be 2.
     ~A[1]---+||
      A[1]--+|||
     ~A[0]-+||||
-     A[0]+||||| 
+     A[0]+|||||
          |||||| product formula
          010000 ~\A[0]
          001001 \A[1]~\A[2]
@@ -43,4 +43,4 @@ values.
 .. autocellgroup:: logic
    :members:
    :source:
-   :linenos:
+   :linenos:

docs/source/cmd/index_internal.rst

@@ -88,7 +88,7 @@ Dumping command help to json
       by ``Pass::experimental()``)
     * also title (``short_help`` argument in ``Pass::Pass``), group, and class
       name
-   
+
   + dictionary of group name to list of commands in that group
 
 - used by sphinx autodoc to generate help content
@@ -106,7 +106,7 @@ Dumping command help to json
    code block is formatted as ``yoscrypt`` (e.g. `synth_ice40`).  The caveat
    here is that if the ``script()`` calls ``run()`` on any commands *prior* to
    the first ``check_label`` then the auto detection will break and revert to
-   unformatted code (e.g. `synth_fabulous`). 
+   unformatted code (e.g. `synth_fabulous`).
 
 Command line rendering
 ~~~~~~~~~~~~~~~~~~~~~~
@@ -114,7 +114,7 @@ Command line rendering
 - if ``Pass::formatted_help()`` returns true, will call
   ``PrettyHelp::log_help()``
 
-  + traverse over the children of the root node and render as plain text 
+  + traverse over the children of the root node and render as plain text
   + effectively the reverse of converting unformatted ``Pass::help()`` text
   + lines are broken at 80 characters while maintaining indentation (controlled
     by ``MAX_LINE_LEN`` in :file:`kernel/log_help.cc`)

docs/source/code_examples/fifo/Makefile

@@ -2,7 +2,7 @@ include ../../../common.mk
 
 DOT_NAMES = addr_gen_hier addr_gen_proc addr_gen_clean
 DOT_NAMES += rdata_proc rdata_flat rdata_adffe rdata_memrdv2 rdata_alumacc rdata_coarse
-MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates 
+MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates
 MAPDOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells
 
 DOTS := $(addsuffix .dot,$(DOT_NAMES))

docs/source/code_examples/fifo/fifo.v

@@ -1,5 +1,5 @@
 // address generator/counter
-module addr_gen 
+module addr_gen
 #(  parameter MAX_DATA=256,
 	localparam AWIDTH = $clog2(MAX_DATA)
 ) ( input en, clk, rst,
@@ -21,7 +21,7 @@ module addr_gen
 endmodule //addr_gen
 
 // Define our top level fifo entity
-module fifo 
+module fifo
 #(  parameter MAX_DATA=256,
 	localparam AWIDTH = $clog2(MAX_DATA)
 ) ( input wen, ren, clk, rst,

docs/source/code_examples/fifo/fifo.ys

@@ -2,7 +2,7 @@
 # throw in some extra text to match what we expect if we were opening an
 # interactive terminal
 log $ yosys fifo.v
-log 
+log
 log -- Parsing `fifo.v' using frontend ` -vlog2k' --
 read_verilog -defer fifo.v
 

docs/source/code_examples/intro/mycells.v

@@ -20,4 +20,3 @@ output reg Q;
 always @(posedge C)
 	Q <= D;
 endmodule
-

docs/source/code_examples/macc/Makefile

@@ -16,4 +16,3 @@ macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys
 .PHONY: clean
 clean:
 	@rm -f *.dot
-

docs/source/code_examples/macc/macc_xilinx_test.ys

@@ -50,4 +50,3 @@ show -prefix macc_xilinx_test2e -format dot -notitle test2
 
 design -load __macc_xilinx_xmap
 show -prefix macc_xilinx_xmap -format dot -notitle
-

docs/source/code_examples/macro_commands/synth_ice40.ys

@@ -54,7 +54,7 @@ map_gates:
     ice40_wrapcarry
     techmap
     opt -fast
-    abc -dff -D 1 
+    abc -dff -D 1
     ice40_opt
 
 map_ffs:
@@ -89,4 +89,3 @@ check:
     stat
     check -noinit
     blackbox =A:whitebox
-        

docs/source/code_examples/opt/opt_expr.ys

@@ -3,7 +3,7 @@ read_verilog <<EOT
 module uut(
     input a,
     output y, z
-);  
+);
     assign y = a == a;
     assign z = a != a;
 endmodule

docs/source/code_examples/opt/opt_merge.ys

@@ -15,4 +15,3 @@ opt_merge after
 clean
 
 show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut
-

docs/source/code_examples/opt/opt_muxtree.ys

@@ -3,7 +3,7 @@ read_verilog <<EOT
 module uut(
     input a, b, c, d,
     output y
-);  
+);
     assign y = a ? (a ? b : c) : d;
 endmodule
 
@@ -14,4 +14,3 @@ opt_muxtree after
 clean
 
 show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut
-

docs/source/code_examples/scrambler/scrambler.ys

@@ -19,4 +19,3 @@ eval -set in 1 -show out
 eval -set in 270369 -show out
 
 sat -set out 632435482
-

docs/source/code_examples/show/cmos.ys

@@ -2,7 +2,7 @@
 read_verilog cmos.v
 prep -top cmos_demo
 techmap
-abc -liberty ../intro/mycells.lib;; 
+abc -liberty ../intro/mycells.lib;;
 show -format dot -prefix cmos_00
 
 # reset
@@ -13,5 +13,5 @@ read_verilog cmos.v
 prep -top cmos_demo
 techmap
 splitnets -ports
-abc -liberty ../intro/mycells.lib;; 
+abc -liberty ../intro/mycells.lib;;
 show -lib ../intro/mycells.v -format dot -prefix cmos_01

docs/source/code_examples/synth_flow/Makefile

@@ -17,4 +17,3 @@ examples:
 .PHONY: clean
 clean:
 	@rm -f *.dot
-

docs/source/getting_started/example_synth.rst

@@ -199,7 +199,7 @@ opt_expr <adv_opt_expr>`.
 .. todo:: consider a brief glossary for terms like adff
 
 .. seealso:: Advanced usage docs for
-   
+
    - :doc:`/using_yosys/synthesis/proc`
    - :doc:`/using_yosys/synthesis/opt`
 
@@ -321,7 +321,7 @@ and merged with the ``raddr`` wire feeding into the `$memrd` cell.  This wire
 merging happened during the call to `clean` which we can see in the
 :ref:`flat_clean`.
 
-.. note:: 
+.. note::
 
    `flatten` and `clean` would normally be combined into a
    single :yoterm:`yosys> flatten;;` output, but they appear separately here as
@@ -394,7 +394,7 @@ highlighted below:
    ``rdata`` output after `opt_dff`
 
 .. seealso:: Advanced usage docs for
-   
+
    - :doc:`/using_yosys/synthesis/fsm`
    - :doc:`/using_yosys/synthesis/opt`
 
@@ -461,7 +461,7 @@ memory read with appropriate enable (``EN=1'1``) and reset (``ARST=1'0`` and
 ``SRST=1'0``) inputs.
 
 .. seealso:: Advanced usage docs for
-   
+
    - :doc:`/using_yosys/synthesis/opt`
    - :doc:`/using_yosys/synthesis/techmap_synth`
    - :doc:`/using_yosys/synthesis/memory`
@@ -659,7 +659,7 @@ into flip flops (the ``logic fallback``) with `memory_map`.
    complex.
 
 .. seealso:: Advanced usage docs for
-   
+
    - :doc:`/using_yosys/synthesis/techmap_synth`
    - :doc:`/using_yosys/synthesis/memory`
 
@@ -757,7 +757,7 @@ cells.
    ``rdata`` output after :ref:`map_cells`
 
 .. seealso:: Advanced usage docs for
-   
+
    - :doc:`/using_yosys/synthesis/techmap_synth`
    - :doc:`/using_yosys/synthesis/abc`
 

docs/source/getting_started/installation.rst

@@ -152,7 +152,7 @@ Installing all prerequisites:
       recommended to use Windows Subsystem for Linux (WSL) and follow the
       instructions for Ubuntu.
 
-.. 
+..
    tab:: MSYS2 (MINGW64)
 
    .. code:: console

docs/source/getting_started/scripting_intro.rst

@@ -149,11 +149,11 @@ represent, see :ref:`interactive_show` and the
 
    Calling :yoscrypt:`show addr_gen` after `hierarchy`
 
-.. note:: 
+.. note::
 
    The `show` command requires a working installation of `GraphViz`_ and `xdot`_
    for displaying the actual circuit diagrams.
-   
+
 .. _GraphViz: http://www.graphviz.org/
 .. _xdot: https://github.com/jrfonseca/xdot.py
 

docs/source/introduction.rst

@@ -125,7 +125,7 @@ The first version of the Yosys documentation was published as a bachelor thesis
 at the Vienna University of Technology :cite:p:`BACC`.
 
 :Abstract:
-	Most of today's digital design is done in HDL code (mostly Verilog or 
+	Most of today's digital design is done in HDL code (mostly Verilog or
 	VHDL) and with the help of HDL synthesis tools.
 
 	In special cases such as synthesis for coarse-grain cell libraries or
@@ -164,14 +164,14 @@ for specialised tasks.
 Benefits of open source HDL synthesis
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-- Cost (also applies to ``free as in free beer`` solutions): 
+- Cost (also applies to ``free as in free beer`` solutions):
-  
+
   Today the cost for a mask set in 180nm technology is far less than the cost
   for the design tools needed to design the mask layouts. Open Source ASIC flows
   are an important enabler for ASIC-level Open Source Hardware.
 
-- Availability and Reproducibility: 
+- Availability and Reproducibility:
-  
+
   If you are a researcher who is publishing, you want to use tools that everyone
   else can also use. Even if most universities have access to all major
   commercial tools, you usually do not have easy access to the version that was
@@ -179,14 +179,14 @@ Benefits of open source HDL synthesis
   can even release the source code of the tool you have used alongside your
   data.
 
-- Framework: 
+- Framework:
-  
+
   Yosys is not only a tool. It is a framework that can be used as basis for
   other developments, so researchers and hackers alike do not need to re-invent
   the basic functionality. Extensibility was one of Yosys' design goals.
 
-- All-in-one: 
+- All-in-one:
-  
+
   Because of the framework characteristics of Yosys, an increasing number of
   features become available in one tool. Yosys not only can be used for circuit
   synthesis but also for formal equivalence checking, SAT solving, and for
@@ -194,8 +194,8 @@ Benefits of open source HDL synthesis
   proprietary software one needs to learn a new tool for each of these
   applications.
 
-- Educational Tool: 
+- Educational Tool:
-  
+
   Proprietary synthesis tools are at times very secretive about their inner
   workings. They often are ``black boxes``. Yosys is very open about its
   internals and it is easy to observe the different steps of synthesis.

docs/source/literature.bib

@@ -66,24 +66,24 @@
 	year = {1996}
 }
 
-@ARTICLE{Verilog2005, 
+@ARTICLE{Verilog2005,
 	journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)},
-	title={IEEE Standard for Verilog Hardware Description Language}, 
+	title={IEEE Standard for Verilog Hardware Description Language},
 	author={IEEE Standards Association and others},
-	year={2006}, 
+	year={2006},
 	doi={10.1109/IEEESTD.2006.99495}
 }
 
-@ARTICLE{VerilogSynth, 
+@ARTICLE{VerilogSynth,
 	journal={IEEE Std 1364.1-2002},
-	title={IEEE Standard for Verilog Register Transfer Level Synthesis}, 
+	title={IEEE Standard for Verilog Register Transfer Level Synthesis},
 	author={IEEE Standards Association and others},
-	year={2002}, 
+	year={2002},
 	doi={10.1109/IEEESTD.2002.94220}
 }
 
 @ARTICLE{VHDL,
-	journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, 
+	journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)},
 	title={IEEE Standard VHDL Language Reference Manual},
 	author={IEEE Standards Association and others},
 	year={2009},
@@ -92,20 +92,20 @@
 }
 
 @ARTICLE{VHDLSynth,
-	journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, 
+	journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)},
 	title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis},
 	author={IEEE Standards Association and others},
 	year={2004},
 	doi={10.1109/IEEESTD.2004.94802}
 }
 
-@ARTICLE{IP-XACT, 
+@ARTICLE{IP-XACT,
-	journal={IEEE Std 1685-2009}, 
+	journal={IEEE Std 1685-2009},
-	title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, 
+	title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows},
 	author={IEEE Standards Association and others},
-	year={2010}, 
+	year={2010},
-	pages={C1-360}, 
+	pages={C1-360},
-	keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, 
+	keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema},
 	doi={10.1109/IEEESTD.2010.5417309}
 }
 
@@ -116,7 +116,7 @@
 	isbn = {0-201-10088-6},
 	publisher = {Addison-Wesley Longman Publishing Co., Inc.},
 	address = {Boston, MA, USA}
-} 
+}
 
 @INPROCEEDINGS{Cummings00,
 	author = {Clifford E. Cummings and Sunburst Design Inc},
@@ -132,26 +132,26 @@
 	year={August 1967}
 }
 
-@INPROCEEDINGS{fsmextract, 
+@INPROCEEDINGS{fsmextract,
-	author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, 
+	author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren},
-	booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, 
+	booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on},
-	title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, 
+	title={A highly efficient method for extracting FSMs from flattened gate-level netlist},
-	year={2010}, 
+	year={2010},
-	pages={2610-2613}, 
+	pages={2610-2613},
-	keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, 
+	keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing},
 	doi={10.1109/ISCAS.2010.5537093},
 }
 
-@ARTICLE{MultiLevelLogicSynth, 
+@ARTICLE{MultiLevelLogicSynth,
-	author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.}, 
+	author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.},
-	journal={Proceedings of the IEEE}, 
+	journal={Proceedings of the IEEE},
-	title={Multilevel logic synthesis}, 
+	title={Multilevel logic synthesis},
-	year={1990}, 
+	year={1990},
-	volume={78}, 
+	volume={78},
-	number={2}, 
+	number={2},
-	pages={264-300}, 
+	pages={264-300},
-	keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, 
+	keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon},
-	doi={10.1109/5.52213}, 
+	doi={10.1109/5.52213},
 	ISSN={0018-9219},
 }
 
@@ -171,7 +171,7 @@
 	acmid = {321925},
 	publisher = {ACM},
 	address = {New York, NY, USA},
-} 
+}
 
 @article{een2003temporal,
   title={Temporal induction by incremental SAT solving},

docs/source/using_yosys/more_scripting/data_flow_tracking.rst

@@ -111,4 +111,4 @@ For example, an AND gate will propagate a given tag on one input, if the other
 input is either 1 or carries a tag of the same group. So if one input is ``0,
 "key:a"`` and the other is ``0, "key:b"`` the result would be ``0, "key:a",
 "key:b"``, rather than simply ``0``. Note that if we add an unrelated
-``"overflow"`` tag to the first input, it would still not be propagated.
+``"overflow"`` tag to the first input, it would still not be propagated.

docs/source/using_yosys/more_scripting/interactive_investigation.rst

@@ -56,7 +56,7 @@ is shown.
 
 .. figure:: /_images/code_examples/show/example_first.*
    :class: width-helper invert-helper
-   
+
    Output of the first `show` command in :numref:`example_ys`
 
 The first output shows the design directly after being read by the Verilog
@@ -88,7 +88,7 @@ multiplexer and a d-type flip-flop, which brings us to the second diagram:
 
 .. figure:: /_images/code_examples/show/example_second.*
    :class: width-helper invert-helper
-   
+
    Output of the second `show` command in :numref:`example_ys`
 
 The Rhombus shape to the right is a dangling wire. (Wire nodes are only shown if
@@ -106,14 +106,14 @@ operations, it is therefore recommended to always call `clean` before calling
 `show`.
 
 In this script we directly call `opt` as the next step, which finally leads us
-to the third diagram: 
+to the third diagram:
 
 .. figure:: /_images/code_examples/show/example_third.*
    :class: width-helper invert-helper
    :name: example_out
-   
+
    Output of the third `show` command in :ref:`example_ys`
-   
+
 Here we see that the `opt` command not only has removed the artifacts left
 behind by `proc`, but also determined correctly that it can remove the first
 `$mux` cell without changing the behavior of the circuit.
@@ -167,7 +167,7 @@ mapped to a cell library:
    :class: width-helper invert-helper
    :name: first_pitfall
 
-   A half-adder built from simple CMOS gates, demonstrating common pitfalls when 
+   A half-adder built from simple CMOS gates, demonstrating common pitfalls when
    using `show`
 
 .. literalinclude:: /code_examples/show/cmos.ys
@@ -176,7 +176,7 @@ mapped to a cell library:
    :end-at: cmos_00
    :name: pitfall_code
    :caption: Generating :numref:`first_pitfall`
-   
+
 First, Yosys did not have access to the cell library when this diagram was
 generated, resulting in all cell ports defaulting to being inputs. This is why
 all ports are drawn on the left side the cells are awkwardly arranged in a large
@@ -248,7 +248,7 @@ command already fails to verify, it is better to troubleshoot the coarse-grain
 version of the circuit before `techmap` than the gate-level circuit after
 `techmap`.
 
-.. Note:: 
+.. Note::
 
    It is generally recommended to verify the internal state of a design by
    writing it to a Verilog file using :yoscrypt:`write_verilog -noexpr` and
@@ -327,7 +327,7 @@ tools).
 - :cmd:title:`dump`.
 - :cmd:title:`add` and :cmd:title:`delete` can be used to modify and reorganize
   a design dynamically.
-  
+
 The code used is included in the Yosys code base under
 |code_examples/scrambler|_.
 
@@ -438,7 +438,7 @@ Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:
 
 .. figure:: /_images/code_examples/selections/memdemo_00.*
    :class: width-helper invert-helper
-   
+
    ``memdemo``
 
 Because this produces a rather large circuit, it can be useful to split it into
@@ -459,18 +459,18 @@ below.
 
 .. figure:: /_images/code_examples/selections/submod_02.*
    :class: width-helper invert-helper
-   
+
    ``outstage``
 
 .. figure:: /_images/code_examples/selections/submod_03.*
    :class: width-helper invert-helper
    :name: selstage
-   
+
    ``selstage``
 
 .. figure:: /_images/code_examples/selections/submod_01.*
    :class: width-helper invert-helper
-   
+
    ``scramble``
 
 Evaluation of combinatorial circuits
@@ -541,9 +541,9 @@ to solve this kind of problems.
 
 .. _MiniSAT: http://minisat.se/
 
-.. note:: 
+.. note::
-    
+
-    While it is possible to perform model checking directly in Yosys, it 
+    While it is possible to perform model checking directly in Yosys, it
     is highly recommended to use SBY or EQY for formal hardware verification.
 
 The `sat` command works very similar to the `eval` command. The main difference

docs/source/using_yosys/more_scripting/load_design.rst

@@ -81,7 +81,7 @@ Yosys frontends
    'Frontend' here means that the command is implemented as a sub-class of
    ``RTLIL::Frontend``, as opposed to the usual ``RTLIL::Pass``.
 
-.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under 
+.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under
           :doc:`/yosys_internals/extending_yosys/index`
 
 The `read_verilog` command

docs/source/using_yosys/more_scripting/selections.rst

@@ -35,8 +35,8 @@ selection; while :yoscrypt:`delete foobar` will only delete the module foobar.
 If no `select` command has been made, then the "current selection" will be the
 whole design.
 
-.. note:: Many of the examples on this page make use of the `show` 
+.. note:: Many of the examples on this page make use of the `show`
-   command to visually demonstrate the effect of selections.  For a more 
+   command to visually demonstrate the effect of selections.  For a more
    detailed look at this command, refer to :ref:`interactive_show`.
 
 How to make a selection
@@ -106,7 +106,7 @@ glance. When it is called with multiple arguments, each argument is evaluated
 and pushed separately on a stack. After all arguments have been processed it
 simply creates the union of all elements on the stack. So :yoscrypt:`select
 t:$add a:foo` will select all `$add` cells and all objects with the ``foo``
-attribute set:   
+attribute set:
 
 .. literalinclude:: /code_examples/selections/foobaraddsub.v
    :caption: Test module for operations on selections
@@ -130,7 +130,7 @@ select all `$add` cells that have the ``foo`` attribute set:
 
 .. code-block::
    :caption: Output for command ``select t:$add a:foo %i -list`` on :numref:`foobaraddsub`
-   
+
    yosys> select t:$add a:foo %i -list
    foobaraddsub/$add$foobaraddsub.v:4$1
 
@@ -282,7 +282,7 @@ provided :file:`memdemo.v` is in the same directory. We can now change to the
 .. figure:: /_images/code_examples/selections/memdemo_00.*
    :class: width-helper invert-helper
    :name: memdemo_00
-   
+
    Complete circuit diagram for the design shown in :numref:`memdemo_src`
 
 There's a lot going on there, but maybe we are only interested in the tree of
@@ -293,7 +293,7 @@ cones`_ from above, we can use :yoscrypt:`show y %ci2`:
 .. figure:: /_images/code_examples/selections/memdemo_01.*
    :class: width-helper invert-helper
    :name: memdemo_01
-   
+
    Output of :yoscrypt:`show y %ci2`
 
 From this we would learn that ``y`` is driven by a `$dff` cell, that ``y`` is
@@ -305,7 +305,7 @@ start of the name).  Let's go a bit further now and try :yoscrypt:`show y %ci5`:
 .. figure:: /_images/code_examples/selections/memdemo_02.*
    :class: width-helper invert-helper
    :name: memdemo_02
-   
+
    Output of :yoscrypt:`show y %ci5`
 
 That's starting to get a bit messy, so maybe we want to ignore the mux select
@@ -319,7 +319,7 @@ type with :yoscrypt:`show y %ci5:-$mux[S]`:
 .. figure:: /_images/code_examples/selections/memdemo_03.*
    :class: width-helper invert-helper
    :name: memdemo_03
-   
+
    Output of :yoscrypt:`show y %ci5:-$mux[S]`
 
 We could use a command such as :yoscrypt:`show y %ci2:+$dff[Q,D]
@@ -330,7 +330,7 @@ multiplexer select inputs and flip-flop cells:
 .. figure:: /_images/code_examples/selections/memdemo_05.*
    :class: width-helper invert-helper
    :name: memdemo_05
-   
+
    Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff``
 
 Or we could use :yoscrypt:`show y %ci*:-[CLK,S]:+$dff:+$mux` instead, following
@@ -342,7 +342,7 @@ ignoring any ports named ``CLK`` or ``S``:
 .. figure:: /_images/code_examples/selections/memdemo_04.*
    :class: width-helper invert-helper
    :name: memdemo_04
-   
+
    Output of :yoscrypt:`show y %ci*:-[CLK,S]:+$dff,$mux`
 
 Similar to ``%ci`` exists an action ``%co`` to select output cones that accepts

docs/source/using_yosys/synthesis/abc.rst

@@ -178,4 +178,3 @@ of carry chains and DSPs, it avoids optimising for a path that isn't the actual
 critical path, while the generally-longer paths result in ABC9 being able to
 reduce design area by mapping other logic to slower cells with greater logic
 density.
-

docs/source/using_yosys/synthesis/cell_libs.rst

@@ -18,7 +18,7 @@ detail in the :doc:`/getting_started/example_synth` document.
    The :file:`counter.ys` script includes the commands used to generate the
    images in this document.  Code snippets in this document skip these commands;
    including line numbers to allow the reader to follow along with the source.
-   
+
    To learn more about these commands, check out :ref:`interactive_show`.
 
 .. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro
@@ -37,7 +37,7 @@ First, let's quickly look at the design:
 This is a simple counter with reset and enable.  If the reset signal, ``rst``,
 is high then the counter will reset to 0.  Otherwise, if the enable signal,
 ``en``, is high then the ``count`` register will increment by 1 each rising edge
-of the clock, ``clk``.  
+of the clock, ``clk``.
 
 Loading the design
 ~~~~~~~~~~~~~~~~~~

docs/source/using_yosys/synthesis/extract.rst

@@ -24,7 +24,7 @@ Example code can be found in |code_examples/macc|_.
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
     :class: width-helper invert-helper
-    
+
     before `extract`
 
 .. literalinclude:: /code_examples/macc/macc_simple_test.ys
@@ -33,7 +33,7 @@ Example code can be found in |code_examples/macc|_.
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
     :class: width-helper invert-helper
-    
+
     after `extract`
 
 .. literalinclude:: /code_examples/macc/macc_simple_test.v
@@ -228,4 +228,4 @@ Unwrap in ``test2``:
     :end-before: end part e
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
-    :class: width-helper invert-helper
+    :class: width-helper invert-helper

docs/source/using_yosys/synthesis/fsm.rst

@@ -92,7 +92,7 @@ transition table. For each state:
 3. Set the state signal to the current state
 4. Try to evaluate the next state and control output
 5. If step 4 was not successful:
-   
+
    -  Recursively goto step 4 with the offending stop-signal set to 0.
    -  Recursively goto step 4 with the offending stop-signal set to 1.
 

docs/source/using_yosys/synthesis/index.rst

@@ -31,4 +31,3 @@ for commands such as `abc`\ /`abc9`, `simplemap`, `dfflegalize`, and
    extract
    abc
    cell_libs
-

docs/source/using_yosys/synthesis/memory.rst

@@ -122,7 +122,7 @@ to four memory primitive classes available for selection:
   - Can handle arbitrary number and kind of read ports
 
 - LUT RAM (aka distributed RAM): uses LUT storage as RAM
-  
+
   - Supported on most FPGAs (with notable exception of ice40)
   - Usually has one synchronous write port, one or more asynchronous read ports
   - Small
@@ -141,7 +141,7 @@ to four memory primitive classes available for selection:
 - Huge RAM:
 
   - Only supported on several targets:
-    
+
     - Some Xilinx UltraScale devices (UltraRAM)
 
       - Two ports, both with mutually exclusive synchronous read and write
@@ -154,7 +154,7 @@ to four memory primitive classes available for selection:
       - Does not support initial data
 
     - Nexus (large RAM)
-      
+
       - Two ports, both with mutually exclusive synchronous read and write
       - Single clock
 
@@ -304,7 +304,7 @@ Synchronous SDP with undefined collision behavior
 
 		if (read_enable) begin
 			read_data <= mem[read_addr];
-		
+
 		if (write_enable && read_addr == write_addr)
 			// this if block
 			read_data <= 'x;
@@ -322,7 +322,7 @@ Synchronous SDP with undefined collision behavior
 		if (write_enable)
 			mem[write_addr] <= write_data;
 
-		if (read_enable) 
+		if (read_enable)
 			read_data <= mem[read_addr];
 	end
 
@@ -446,7 +446,7 @@ Synchronous single-port RAM with write-first behavior
 		if (read_enable)
 			if (write_enable)
 				read_data <= write_data;
-			else 
+			else
 				read_data <= mem[addr];
 	end
 
@@ -787,4 +787,3 @@ Asynchronous writes
 	end
 
 	assign read_data = mem[read_addr];
-

docs/source/using_yosys/synthesis/techmap_synth.rst

@@ -1,4 +1,4 @@
-Technology mapping 
+Technology mapping
 ==================
 
 .. todo:: less academic, check text is coherent

docs/source/yosys_internals/extending_yosys/advanced_bugpoint.rst

@@ -240,7 +240,7 @@ the design at each log header.
 
 A worked example
 ~~~~~~~~~~~~~~~~
-  
+
 Say you did all the minimization and found that an error in `synth_xilinx`
 occurs when a call to ``techmap -map +/xilinx/cells_map.v`` with
 ``MIN_MUX_INPUTS`` defined parses a `$_MUX16_` with all inputs set to ``1'x``.

docs/source/yosys_internals/extending_yosys/extensions.rst

@@ -68,7 +68,7 @@ with, and lists off the current design's modules.
    :language: c++
    :lines: 1, 4, 6, 7-20
    :caption: Example command :yoscrypt:`my_cmd` from :file:`my_cmd.cc`
-   
+
 Note that we are making a global instance of a class derived from
 ``Yosys::Pass``, which we get by including :file:`kernel/yosys.h`.
 

docs/source/yosys_internals/extending_yosys/index.rst

@@ -14,4 +14,3 @@ of interest for developers looking to customise Yosys builds.
    advanced_bugpoint
    contributing
    test_suites
-

docs/source/yosys_internals/extending_yosys/test_suites.rst

@@ -16,6 +16,20 @@ tests.
    cmake -B build .
    cmake --build build --target test --parallel $(nproc)
 
+.. warning::
+
+   There are limitations when using `Ninja` as generator, so we suggest using
+   `Unix Makefiles` to make running tests in parallel possible. However, it is
+   possible to use it directly by running:
+
+.. code:: console
+
+   cd tests
+   make -j9
+
+Please note that in this case default build directory is `build` but can be
+overwritten by providing `BUILD_DIR` variable.
+
 Vanilla tests
 ~~~~~~~~~~~~~
 
@@ -76,15 +90,19 @@ If you don't have one of the :ref:`getting_started/installation:CAD suite(s)`
 installed, you should also install Z3 `following their
 instructions <https://github.com/Z3Prover/z3>`_.
 
-.. TODO:: CMAKE_TODO
+Functional tests are disabled by default, to enable them use next code snippet
+and run tests as usual:
 
-   How does this work under CMake?  Is it only via ``make -C tests
+.. code:: console
-   ENABLE_FUNCTIONAL_TESTS=1`` and then manually setting ``BUILD_DIR`` and
-   ``PROGRAM_PREFIX``?  And possibly also setting ``YOSYS`` et al if there is a
-   ``.exe``.  Previous instructions:
 
-   Then, set the :makevar:`ENABLE_FUNCTIONAL_TESTS` make variable when calling
+   cmake -B build . -DYOSYS_ENABLE_FUNCTIONAL_TESTS=ON
-   ``make test`` and the functional tests will be run as well.
+   cmake --build build --target test --parallel $(nproc)
+
+Or run just functional tests with:
+
+.. code:: console
+
+   cmake --build build --target test-functional
 
 Docs tests
 ~~~~~~~~~~
@@ -164,6 +182,9 @@ compiler versions.  For up to date information, including OS versions, refer to
    test for ``kernel/celledges.cc``, you will need to create a file like this:
    ``tests/unit/kernel/celledgesTest.cc``;
    * Implement your unit test
+   * Add unit test to file list in `CMakeLists.txt`
+   In case unit tests are added to new directory, note that you need also to
+   create new `CmakeList.txt` file and add ``yosys_gtest(dir-name unit-test.cc)```
 
    Run unit tests
    ~~~~~~~~~~~~~~
@@ -172,10 +193,4 @@ compiler versions.  For up to date information, including OS versions, refer to
 
    .. code-block:: console
 
-      make unit-test
+      cmake --build build --target test-unit
-
-   If you want to remove all unit test files, type:
-
-   .. code-block:: console
-
-      make clean-unit-test

docs/source/yosys_internals/flow/index.rst

@@ -10,10 +10,9 @@ These scripts contain three types of commands:
 - **Backends**, that write the design in memory to a file (various formats are
   available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .).
 
-.. toctree:: 
+.. toctree::
 	:maxdepth: 3
 
 	overview
 	control_and_data
 	verilog_frontend
-

docs/source/yosys_internals/flow/verilog_frontend.rst

@@ -432,12 +432,12 @@ variables:
     initialization of ``AST_INTERNAL::ProcessGenerator`` these two variables are
     empty.
 
--  | ``subst_lvalue_from`` and ``subst_lvalue_to`` 
+-  | ``subst_lvalue_from`` and ``subst_lvalue_to``
    | These two variables contain the mapping from left-hand-side signals (``\
      <name>``) to the current temporary signal for the same thing (initially
      ``$0\ <name>``).
 
--  | ``current_case`` 
+-  | ``current_case``
    | A pointer to a ``RTLIL::CaseRule`` object. Initially this is the root case
      of the generated ``RTLIL::Process``.
 
@@ -603,13 +603,13 @@ behavioural model in ``RTLIL::Process`` representation. The actual conversion
 from a behavioural model to an RTL representation is performed by the `proc`
 pass and the passes it launches:
 
--  | `proc_clean` and `proc_rmdead` 
+-  | `proc_clean` and `proc_rmdead`
    | These two passes just clean up the ``RTLIL::Process`` structure. The
      `proc_clean` pass removes empty parts (eg. empty assignments) from the
      process and `proc_rmdead` detects and removes unreachable branches from the
      process's decision trees.
 
--  | `proc_arst` 
+-  | `proc_arst`
    | This pass detects processes that describe d-type flip-flops with
      asynchronous resets and rewrites the process to better reflect what they
      are modelling: Before this pass, an asynchronous reset has two
@@ -617,7 +617,7 @@ pass and the passes it launches:
      reset path. After this pass the sync rule for the reset is level-sensitive
      and the top-level ``RTLIL::SwitchRule`` has been removed.
 
--  | `proc_mux` 
+-  | `proc_mux`
    | This pass converts the ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule``-tree to
      a tree of multiplexers per written signal. After this, the
      ``RTLIL::Process`` structure only contains the ``RTLIL::SyncRule`` s that

docs/source/yosys_internals/formats/index.rst

@@ -48,7 +48,7 @@ RTLIL and fail to run when unsupported high-level constructs are used. In such
 cases a pass that transforms the higher-level constructs to lower-level
 constructs must be called from the synthesis script first.
 
-.. toctree:: 
+.. toctree::
    :maxdepth: 3
 
    rtlil_rep
@@ -56,4 +56,3 @@ constructs must be called from the synthesis script first.
 .. [1]
    In Yosys the term pass is only used to refer to commands that operate on the
    RTLIL data structure.
-

docs/source/yosys_internals/formats/rtlil_rep.rst

@@ -158,8 +158,8 @@ An ``RTLIL::Wire`` object has the following properties:
 -  The wire name
 -  A list of attributes
 -  A width (buses are just wires with a width more than 1)
--  Bus direction (MSB to LSB or vice versa)
+-  Bus direction (MSb to LSb or vice versa)
--  Lowest valid bit index (LSB or MSB depending on bus direction)
+-  Lowest valid bit index (LSb or MSb depending on bus direction)
 -  If the wire is a port: port number and direction (input/output/inout)
 
 As with modules, the attributes can be Verilog attributes imported by the
@@ -171,8 +171,8 @@ signals. This makes some aspects of RTLIL more complex but enables Yosys to be
 used for coarse grain synthesis where the cells of the target architecture
 operate on entire signal vectors instead of single bit wires.
 
-In Verilog and VHDL, busses may have arbitrary bounds, and LSB can have either
+In Verilog and VHDL, busses may have arbitrary bounds, and LSb can have either
-the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSB;
+the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSb;
 however, information from the HDL frontend is preserved so that the bus will be
 correctly indexed in error messages, backend output, constraint files, etc.
 

docs/tests/macro_commands.py

@@ -94,7 +94,7 @@ for macro in MACRO_SOURCE.glob("*.ys"):
             if expected_dict[key] and expected_dict[key] != actual_dict[key]:
                 does_match = False
 
-        # raise error on mismatch        
+        # raise error on mismatch
         if not does_match:
             logging.error(f"Expected {expected!r}, got {actual!r}")
             raise_error = True

docs/util/RtlilLexer.py

@@ -9,7 +9,7 @@ class RtlilLexer(RegexLexer):
     filenames = ['*.il']
 
     keyword_re = r'(always|assign|attribute|autoidx|case|cell|connect|edge|end|global|high|init|inout|input|low|memory|module|negedge|offset|output|parameter|posedge|process|real|signed|size|switch|sync|update|upto|width|wire)'
-    
+
     tokens = {
         'common': [
             (r'\s+', Whitespace),

docs/util/cell_documenter.py

@@ -34,7 +34,7 @@ class YosysCell:
     inputs: list[str]
     outputs: list[str]
     properties: list[str]
-    
+
 class YosysCellGroupDocumenter(Documenter):
     objtype = 'cellgroup'
     priority = 10
@@ -67,7 +67,7 @@ class YosysCellGroupDocumenter(Documenter):
                 for (name, obj) in cells_obj.get(self.lib_key, {}).items():
                     self.__cell_lib[name] = obj
         return self.__cell_lib
-    
+
     @classmethod
     def can_document_member(
         cls,
@@ -83,7 +83,7 @@ class YosysCellGroupDocumenter(Documenter):
             self.content_indent = ''
         self.fullname = self.modname = self.name
         return True
-    
+
     def import_object(self, raiseerror: bool = False) -> bool:
         # get cell
         try:
@@ -95,16 +95,16 @@ class YosysCellGroupDocumenter(Documenter):
 
         self.real_modname = self.modname
         return True
-    
+
     def get_sourcename(self) -> str:
         return self.env.doc2path(self.env.docname)
-    
+
     def format_name(self) -> str:
         return self.options.caption or ''
 
     def format_signature(self, **kwargs: Any) -> str:
         return self.modname
-    
+
     def add_directive_header(self, sig: str) -> None:
         domain = getattr(self, 'domain', 'cell')
         directive = getattr(self, 'directivetype', 'group')
@@ -118,7 +118,7 @@ class YosysCellGroupDocumenter(Documenter):
 
         if self.options.noindex:
             self.add_line('   :noindex:', sourcename)
-    
+
     def add_content(self, more_content: Any | None) -> None:
         # groups have no native content
         # add additional content (e.g. from document), if present
@@ -271,22 +271,22 @@ class YosysCellDocumenter(YosysCellGroupDocumenter):
         self.fullname = ((self.modname) + (thing or ''))
 
         return True
-    
+
     def import_object(self, raiseerror: bool = False) -> bool:
         if super().import_object(raiseerror):
             self.object = YosysCell(self.modname, **self.object[1])
             return True
         return False
-    
+
     def get_sourcename(self) -> str:
         return self.object.source.split(":")[0]
-    
+
     def format_name(self) -> str:
         return self.object.name
 
     def format_signature(self, **kwargs: Any) -> str:
         return self.groupname + self.fullname + self.attribute
-    
+
     def add_directive_header(self, sig: str) -> None:
         domain = getattr(self, 'domain', self.objtype)
         directive = getattr(self, 'directivetype', 'def')
@@ -310,7 +310,7 @@ class YosysCellDocumenter(YosysCellGroupDocumenter):
 
         if self.options.noindex:
             self.add_line('   :noindex:', sourcename)
-    
+
     def add_content(self, more_content: Any | None) -> None:
         # set sourcename and add content from attribute documentation
         sourcename = self.get_sourcename()
@@ -360,7 +360,7 @@ class YosysCellSourceDocumenter(YosysCellDocumenter):
         if isinstance(parent, YosysCellDocumenter):
             return True
         return False
-    
+
     def add_directive_header(self, sig: str) -> None:
         domain = getattr(self, 'domain', 'cell')
         directive = getattr(self, 'directivetype', 'source')
@@ -383,7 +383,7 @@ class YosysCellSourceDocumenter(YosysCellDocumenter):
 
         if self.options.noindex:
             self.add_line('   :noindex:', sourcename)
-    
+
     def add_content(self, more_content: Any | None) -> None:
         # set sourcename and add content from attribute documentation
         sourcename = self.get_sourcename()

docs/util/cmd_documenter.py

@@ -78,7 +78,7 @@ class YosysCmd:
         self.source_func = source_func
         self.experimental_flag = experimental_flag
         self.internal_flag = internal_flag
-    
+
 class YosysCmdGroupDocumenter(Documenter):
     objtype = 'cmdgroup'
     priority = 10
@@ -112,7 +112,7 @@ class YosysCmdGroupDocumenter(Documenter):
             for (name, obj) in cmds_obj.get(self.lib_key, {}).items():
                 self.__cmd_lib[name] = obj
         return self.__cmd_lib
-    
+
     @classmethod
     def can_document_member(
         cls,
@@ -128,7 +128,7 @@ class YosysCmdGroupDocumenter(Documenter):
             self.content_indent = ''
         self.fullname = self.modname = self.name
         return True
-    
+
     def import_object(self, raiseerror: bool = False) -> bool:
         # get cmd
         try:
@@ -140,19 +140,19 @@ class YosysCmdGroupDocumenter(Documenter):
 
         self.real_modname = self.modname
         return True
-    
+
     def get_sourcename(self) -> str:
         return self.env.doc2path(self.env.docname)
-    
+
     def format_name(self) -> str:
         return self.options.caption or ''
 
     def format_signature(self, **kwargs: Any) -> str:
         return self.modname
-    
+
     def add_directive_header(self, sig: str) -> None:
         pass
-    
+
     def add_content(self, more_content: Any | None) -> None:
         pass
 
@@ -323,7 +323,7 @@ class YosysCmdDocumenter(YosysCmdGroupDocumenter):
             return self.object.source_file
         except AttributeError:
             return super().get_sourcename()
-    
+
     def format_name(self) -> str:
         return self.object.name
 
@@ -347,7 +347,7 @@ class YosysCmdDocumenter(YosysCmdGroupDocumenter):
 
         if self.options.noindex:
             self.add_line('   :noindex:', source_name)
-    
+
     def add_content(self, more_content: Any | None) -> None:
         # set sourcename and add content from attribute documentation
         domain = getattr(self, 'domain', self.objtype)

docs/util/custom_directives.py

@@ -21,7 +21,7 @@ from sphinx.util.nodes import make_refnode
 from sphinx.util.docfields import Field, GroupedField
 from sphinx import addnodes
 
-class TocNode(ObjectDescription):    
+class TocNode(ObjectDescription):
     def add_target_and_index(
         self,
         name: str,
@@ -64,7 +64,7 @@ class NodeWithOptions(TocNode):
     doc_field_types = [
         GroupedField('opts', label='Options', names=('option', 'options', 'opt', 'opts')),
     ]
-    
+
     def transform_content(self, contentnode: addnodes.desc_content) -> None:
         """hack `:option -thing: desc` into a proper option list with yoscrypt highlighting"""
         newchildren = []
@@ -290,7 +290,7 @@ class CellNode(TocNode):
                          self.env.docname,
                          idx,
                          0))
-            
+
     def transform_content(self, contentnode: addnodes.desc_content) -> None:
         # Add the cell title to the body
         if 'title' in self.options:
@@ -380,7 +380,7 @@ class CellSourceNode(TocNode):
                     # only add target and index entry if this is the first
                     # description of the object with this name in this desc block
                     self.add_target_and_index(name, sig, signode)
-        
+
         # handle code
         code = '\n'.join(self.content)
         literal: Element = nodes.literal_block(code, code)
@@ -420,11 +420,11 @@ class CellGroupNode(TocNode):
 
 class TagIndex(Index):
     """A custom directive that creates a tag matrix."""
-    
+
     name = 'tag'
     localname = 'Tag Index'
     shortname = 'Tag'
-    
+
     def __init__(self, *args, **kwargs):
         super(TagIndex, self).__init__(*args, **kwargs)
 
@@ -458,14 +458,14 @@ class TagIndex(Index):
         objs = {name: (dispname, typ, docname, anchor)
                 for name, dispname, typ, docname, anchor, prio
                 in self.domain.get_objects()}
-        
+
         tmap = {}
         tags = self.domain.data[f'obj2{self.name}']
         for name, tags in tags.items():
             for tag in tags:
                 tmap.setdefault(tag,[])
                 tmap[tag].append(name)
-            
+
         for tag in tmap.keys():
             lis = content.setdefault(tag, [])
             objlis = tmap[tag]
@@ -480,11 +480,11 @@ class TagIndex(Index):
 
         return (ret, True)
 
-class CommandIndex(Index):    
+class CommandIndex(Index):
     name = 'cmd'
     localname = 'Command Reference'
     shortname = 'Command'
-    
+
     def __init__(self, *args, **kwargs):
         super(CommandIndex, self).__init__(*args, **kwargs)
 
@@ -525,7 +525,7 @@ class CommandIndex(Index):
             lis.append((
                 dispname, 0, docname,
                 anchor,
-                '', '', title 
+                '', '', title
             ))
         ret = [(k, v) for k, v in sorted(content.items())]
 
@@ -538,7 +538,7 @@ class CellIndex(CommandIndex):
 
 class PropIndex(TagIndex):
     """A custom directive that creates a properties matrix."""
-    
+
     name = 'prop'
     localname = 'Property Index'
     shortname = 'Prop'
@@ -659,7 +659,7 @@ class CommandDomain(Domain):
         else:
             print(f"Missing ref for {target} in {fromdocname} ")
             return None
-        
+
 class CellDomain(CommandDomain):
     name = 'cell'
     label = 'Yosys internal cells'
@@ -730,8 +730,8 @@ def setup(app: Sphinx):
         ('cell-prop', '')
 
     app.add_role('autoref', autoref)
-    
+
     return {
-        'version': '0.3',    
+        'version': '0.3',
         'parallel_read_safe': False,
     }

examples/basys3/README

@@ -16,4 +16,3 @@ Programming board:
 
 All of the above:
   bash run.sh
-

examples/basys3/example.xdc

@@ -21,4 +21,3 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
 
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property CFGBVS VCCO [current_design]
-

examples/cmos/README

@@ -10,4 +10,3 @@ Each test bench can be run separately by either running:
 
 The later case also includes pure verilog simulation using the iverilog
 and gtkwave for comparison.
-

examples/cmos/cmos_cells.sp

@@ -36,4 +36,3 @@ X1 nC D t DLATCH
 X2 C t Q DLATCH
 X3 C nC NOT
 .ENDS DFF
-

examples/cmos/cmos_cells.v

@@ -41,4 +41,3 @@ always @(posedge C, posedge S, posedge R)
 	else
 		Q <= D;
 endmodule
-

examples/cmos/cmos_cells_digital.sp

@@ -28,4 +28,3 @@ Alatch D E null null Q nQ latch1
 .model dff1 d_dff
 Adff D C null null Q nQ dff1
 .ENDS DFF
-

examples/cmos/counter_digital.ys

@@ -13,4 +13,3 @@ abc -liberty cmos_cells.lib;;
 
 write_verilog synth.v
 write_spice -neg 0s -pos 1s synth.sp
-

examples/cmos/testbench.sh

@@ -4,4 +4,3 @@ set -ex
 
 ../../yosys counter.ys
 ngspice testbench.sp
-

examples/cmos/testbench_digital.sh

@@ -12,4 +12,3 @@ iverilog -o counter_tb counter.v counter_tb.v
 
 # requires ngspice with xspice support enabled:
 ngspice testbench_digital.sp
-

examples/cxx-api/demomain.cc

@@ -19,4 +19,3 @@ int main()
 	Yosys::yosys_shutdown();
 	return 0;
 }
-

examples/gowin/README

@@ -14,4 +14,3 @@ gowinTool_linux directory
 
 3.) edit gowinTool_linux/bin/gwlicense.ini. Set lic="..." to
 the full path to the license file.
-

examples/gowin/demo.cst

@@ -7,4 +7,4 @@ IO_LOC "leds[3]" 82;
 IO_LOC "leds[4]" 83;
 IO_LOC "leds[5]" 84;
 IO_LOC "leds[6]" 85;
-IO_LOC "leds[7]" 86;
+IO_LOC "leds[7]" 86;

examples/intel/DE2i-150/quartus_compile/de2i.qsf

@@ -1096,4 +1096,4 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top