luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 14:17:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

Add "whitebox" attribute, add "read_verilog -wb"

Browse Source 
Signed-off-by: Clifford Wolf <[email protected]>
This commit is contained in:
Clifford Wolf
2019-04-18 17:45:47 +02:00
parent ea8ac0aaad
commit f4abc21d8a
23 changed files with 81 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files
passes/cmds/add.cc
+1 -1
View File
@@ -71,7 +71,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
RTLIL::Module *mod = design->modules_.at(it.second->type);
if (!design->selected_whole_module(mod->name))
continue;
if (mod->get_bool_attribute("\\blackbox"))
if (mod->get_blackbox_attribute())
continue;
if (it.second->hasPort(name))
continue;