equiv_simple, equiv_induct: fix config

passes/equiv/equiv.h

@@ -23,13 +23,7 @@ static void report_missing_model(bool warn_only, RTLIL::Cell* cell)
 	}
 }
 
-struct EquivWorker {
+struct EquivBasicConfig {
-	RTLIL::Module *module;
-
-    ezSatPtr ez;
-	SatGen satgen;
-
-    struct Config {
 	bool model_undef = false;
 	int max_seq = 1;
 	bool set_assumes = false;
@@ -69,7 +63,14 @@ struct EquivWorker {
 		"        ignore all cells that can not be matched to a SAT model\n"
 		, default_seq);
 	}
-    };
+};
+
+template<typename Config = EquivBasicConfig>
+struct EquivWorker {
+	RTLIL::Module *module;
+
+	ezSatPtr ez;
+	SatGen satgen;
 	Config cfg;
 
 	EquivWorker(RTLIL::Module *module, const SigMap *sigmap, Config cfg) : module(module), satgen(ez.get(), sigmap), cfg(cfg) {

passes/equiv/equiv_induct.cc

@@ -23,7 +23,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-struct EquivInductWorker : public EquivWorker
+struct EquivInductWorker : public EquivWorker<>
 {
 	SigMap sigmap;
 
@@ -35,7 +35,7 @@ struct EquivInductWorker : public EquivWorker
 	dict<int, int> ez_step_is_consistent;
 	SigPool undriven_signals;
 
-	EquivInductWorker(Module *module, const pool<Cell*> &unproven_equiv_cells, Config cfg) : EquivWorker(module, &sigmap, cfg), sigmap(module),
+	EquivInductWorker(Module *module, const pool<Cell*> &unproven_equiv_cells, EquivBasicConfig cfg) : EquivWorker<>(module, &sigmap, cfg), sigmap(module),
 			cells(module->selected_cells()), workset(unproven_equiv_cells),
 			success_counter(0) {}
 
@@ -174,7 +174,7 @@ struct EquivInductPass : public Pass {
 		log("Only selected $equiv cells are proven and only selected cells are used to\n");
 		log("perform the proof.\n");
 		log("\n");
-		EquivWorker::Config::help("4");
+		EquivBasicConfig::help("4");
 		log("\n");
 		log("This command is very effective in proving complex sequential circuits, when\n");
 		log("the internal state of the circuit quickly propagates to $equiv cells.\n");
@@ -192,7 +192,7 @@ struct EquivInductPass : public Pass {
 	void execute(std::vector<std::string> args, Design *design) override
 	{
 		int success_counter = 0;
-		EquivWorker::Config cfg;
+		EquivBasicConfig cfg {};
 		cfg.max_seq = 4;
 
 		log_header(design, "Executing EQUIV_INDUCT pass.\n");

passes/equiv/equiv_simple.cc

@@ -24,14 +24,12 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-struct EquivSimpleWorker : public EquivWorker
+struct EquivSimpleConfig : EquivBasicConfig {
-{
-	struct Config : EquivWorker::Config {
 	bool verbose = false;
 	bool short_cones = false;
 	bool group = true;
 	bool parse(const std::vector<std::string>& args, size_t& idx) {
-			if (EquivWorker::Config::parse(args, idx))
+		if (EquivBasicConfig::parse(args, idx))
 			return true;
 		if (args[idx] == "-v") {
 			verbose = true;
@@ -48,7 +46,7 @@ struct EquivSimpleWorker : public EquivWorker
 		return false;
 	}
 	static std::string help(const char* default_seq) {
-			return EquivWorker::Config::help(default_seq) +
+		return EquivBasicConfig::help(default_seq) +
 		"    -v\n"
 		"        verbose output\n"
 		"\n"
@@ -60,9 +58,10 @@ struct EquivSimpleWorker : public EquivWorker
 		"        disabling grouping of $equiv cells by output wire\n"
 		"\n";
 	}
-	};
+};
-	Config cfg;
 
+struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
+{
 	const vector<Cell*> &equiv_cells;
 	const vector<Cell*> &assume_cells;
 	struct Cone {
@@ -82,8 +81,8 @@ struct EquivSimpleWorker : public EquivWorker
 
 	pool<pair<Cell*, int>> imported_cells_cache;
 
-	EquivSimpleWorker(const vector<Cell*> &equiv_cells, const vector<Cell*> &assume_cells, DesignModel model, Config cfg) :
+	EquivSimpleWorker(const vector<Cell*> &equiv_cells, const vector<Cell*> &assume_cells, DesignModel model, EquivSimpleConfig cfg) :
-			EquivWorker(equiv_cells.front()->module, &model.sigmap, cfg), equiv_cells(equiv_cells), assume_cells(assume_cells),
+			EquivWorker<EquivSimpleConfig>(equiv_cells.front()->module, &model.sigmap, cfg), equiv_cells(equiv_cells), assume_cells(assume_cells),
 			model(model) {}
 
 	struct ConeFinder {
@@ -270,7 +269,9 @@ struct EquivSimpleWorker : public EquivWorker
 	}
 	void construct_ezsat(const pool<SigBit>& input_bits, int step)
 	{
+		log("ezsat\n");
 		if (cfg.set_assumes) {
+			log("yep assume\n");
 			if (cfg.verbose && step == cfg.max_seq) {
 				RTLIL::SigSpec assumes_a, assumes_en;
 				satgen.getAssumes(assumes_a, assumes_en, step+1);
@@ -427,12 +428,12 @@ struct EquivSimplePass : public Pass {
 		log("\n");
 		log("This command tries to prove $equiv cells using a simple direct SAT approach.\n");
 		log("\n");
-		EquivSimpleWorker::Config::help("1");
+		EquivSimpleConfig::help("1");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, Design *design) override
 	{
-		EquivSimpleWorker::Config cfg = {};
+		EquivSimpleConfig cfg {};
 		int success_counter = 0;
 
 		log_header(design, "Executing EQUIV_SIMPLE pass.\n");