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equiv_simple, equiv_induct: fix config

This commit is contained in:
Emil J. Tywoniak 2026-02-03 18:37:39 +01:00
parent c768e55983
commit ed53ff2f49
3 changed files with 90 additions and 88 deletions
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15
passes/equiv/equiv.h
View File

@ -23,13 +23,7 @@ static void report_missing_model(bool warn_only, RTLIL::Cell* cell)
} }
} }
struct EquivWorker { struct EquivBasicConfig {
RTLIL::Module *module;
ezSatPtr ez;
SatGen satgen;
struct Config {
bool model_undef = false; bool model_undef = false;
int max_seq = 1; int max_seq = 1;
bool set_assumes = false; bool set_assumes = false;
@ -70,6 +64,13 @@ struct EquivWorker {
, default_seq); , default_seq);
} }
}; };
template<typename Config = EquivBasicConfig>
struct EquivWorker {
RTLIL::Module *module;
ezSatPtr ez;
SatGen satgen;
Config cfg; Config cfg;
EquivWorker(RTLIL::Module *module, const SigMap *sigmap, Config cfg) : module(module), satgen(ez.get(), sigmap), cfg(cfg) { EquivWorker(RTLIL::Module *module, const SigMap *sigmap, Config cfg) : module(module), satgen(ez.get(), sigmap), cfg(cfg) {

8
passes/equiv/equiv_induct.cc
View File

@ -23,7 +23,7 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct EquivInductWorker : public EquivWorker struct EquivInductWorker : public EquivWorker<>
{ {
SigMap sigmap; SigMap sigmap;
@ -35,7 +35,7 @@ struct EquivInductWorker : public EquivWorker
dict<int, int> ez_step_is_consistent; dict<int, int> ez_step_is_consistent;
SigPool undriven_signals; SigPool undriven_signals;
EquivInductWorker(Module *module, const pool<Cell*> &unproven_equiv_cells, Config cfg) : EquivWorker(module, &sigmap, cfg), sigmap(module), EquivInductWorker(Module *module, const pool<Cell*> &unproven_equiv_cells, EquivBasicConfig cfg) : EquivWorker<>(module, &sigmap, cfg), sigmap(module),
cells(module->selected_cells()), workset(unproven_equiv_cells), cells(module->selected_cells()), workset(unproven_equiv_cells),
success_counter(0) {} success_counter(0) {}
@ -174,7 +174,7 @@ struct EquivInductPass : public Pass {
log("Only selected $equiv cells are proven and only selected cells are used to\n"); log("Only selected $equiv cells are proven and only selected cells are used to\n");
log("perform the proof.\n"); log("perform the proof.\n");
log("\n"); log("\n");
EquivWorker::Config::help("4"); EquivBasicConfig::help("4");
log("\n"); log("\n");
log("This command is very effective in proving complex sequential circuits, when\n"); log("This command is very effective in proving complex sequential circuits, when\n");
log("the internal state of the circuit quickly propagates to $equiv cells.\n"); log("the internal state of the circuit quickly propagates to $equiv cells.\n");
@ -192,7 +192,7 @@ struct EquivInductPass : public Pass {
void execute(std::vector<std::string> args, Design *design) override void execute(std::vector<std::string> args, Design *design) override
{ {
int success_counter = 0; int success_counter = 0;
EquivWorker::Config cfg; EquivBasicConfig cfg {};
cfg.max_seq = 4; cfg.max_seq = 4;
log_header(design, "Executing EQUIV_INDUCT pass.\n"); log_header(design, "Executing EQUIV_INDUCT pass.\n");

21
passes/equiv/equiv_simple.cc
View File

@ -24,14 +24,12 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct EquivSimpleWorker : public EquivWorker struct EquivSimpleConfig : EquivBasicConfig {
{
struct Config : EquivWorker::Config {
bool verbose = false; bool verbose = false;
bool short_cones = false; bool short_cones = false;
bool group = true; bool group = true;
bool parse(const std::vector<std::string>& args, size_t& idx) { bool parse(const std::vector<std::string>& args, size_t& idx) {
if (EquivWorker::Config::parse(args, idx)) if (EquivBasicConfig::parse(args, idx))
return true; return true;
if (args[idx] == "-v") { if (args[idx] == "-v") {
verbose = true; verbose = true;
@ -48,7 +46,7 @@ struct EquivSimpleWorker : public EquivWorker
return false; return false;
} }
static std::string help(const char* default_seq) { static std::string help(const char* default_seq) {
return EquivWorker::Config::help(default_seq) + return EquivBasicConfig::help(default_seq) +
" -v\n" " -v\n"
" verbose output\n" " verbose output\n"
"\n" "\n"
@ -61,8 +59,9 @@ struct EquivSimpleWorker : public EquivWorker
"\n"; "\n";
} }
}; };
Config cfg;
struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
{
const vector<Cell*> &equiv_cells; const vector<Cell*> &equiv_cells;
const vector<Cell*> &assume_cells; const vector<Cell*> &assume_cells;
struct Cone { struct Cone {
@ -82,8 +81,8 @@ struct EquivSimpleWorker : public EquivWorker
pool<pair<Cell*, int>> imported_cells_cache; pool<pair<Cell*, int>> imported_cells_cache;
EquivSimpleWorker(const vector<Cell*> &equiv_cells, const vector<Cell*> &assume_cells, DesignModel model, Config cfg) : EquivSimpleWorker(const vector<Cell*> &equiv_cells, const vector<Cell*> &assume_cells, DesignModel model, EquivSimpleConfig cfg) :
EquivWorker(equiv_cells.front()->module, &model.sigmap, cfg), equiv_cells(equiv_cells), assume_cells(assume_cells), EquivWorker<EquivSimpleConfig>(equiv_cells.front()->module, &model.sigmap, cfg), equiv_cells(equiv_cells), assume_cells(assume_cells),
model(model) {} model(model) {}
struct ConeFinder { struct ConeFinder {
@ -270,7 +269,9 @@ struct EquivSimpleWorker : public EquivWorker
} }
void construct_ezsat(const pool<SigBit>& input_bits, int step) void construct_ezsat(const pool<SigBit>& input_bits, int step)
{ {
log("ezsat\n");
if (cfg.set_assumes) { if (cfg.set_assumes) {
log("yep assume\n");
if (cfg.verbose && step == cfg.max_seq) { if (cfg.verbose && step == cfg.max_seq) {
RTLIL::SigSpec assumes_a, assumes_en; RTLIL::SigSpec assumes_a, assumes_en;
satgen.getAssumes(assumes_a, assumes_en, step+1); satgen.getAssumes(assumes_a, assumes_en, step+1);
@ -427,12 +428,12 @@ struct EquivSimplePass : public Pass {
log("\n"); log("\n");
log("This command tries to prove $equiv cells using a simple direct SAT approach.\n"); log("This command tries to prove $equiv cells using a simple direct SAT approach.\n");
log("\n"); log("\n");
EquivSimpleWorker::Config::help("1"); EquivSimpleConfig::help("1");
log("\n"); log("\n");
} }
void execute(std::vector<std::string> args, Design *design) override void execute(std::vector<std::string> args, Design *design) override
{ {
EquivSimpleWorker::Config cfg = {}; EquivSimpleConfig cfg {};
int success_counter = 0; int success_counter = 0;
log_header(design, "Executing EQUIV_SIMPLE pass.\n"); log_header(design, "Executing EQUIV_SIMPLE pass.\n");