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Smallfixes

This commit is contained in:
Akash Levy 2025-09-09 04:50:57 -07:00
parent 6fc38e15a1
commit eb4539f151
2 changed files with 7 additions and 7 deletions
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6
passes/opt/wreduce.cc
View File

@ -482,14 +482,14 @@ struct WreduceWorker
SigBit bit(mi.sigmap(conn.second[i]));
bit_drivers_db[bit] = tuple<IdString,IdString>(cell->name, conn.first);
}
} }
}
}
// Build wire mapping for dependency tracking
dict<SigBit, Wire*> bit_to_wire_map;
for (auto w : module->wires()) {
for (auto w : module->wires())
for (auto bit : mi.sigmap(w))
bit_to_wire_map[bit] = w;
}
// Create unified topological sort for both cells and wires
TopoSort<IdString, RTLIL::sort_by_id_str> unified_toposort;

8
tests/silimate/opt_balance_tree.ys
View File

@ -99,7 +99,7 @@ select @c_cells @y_cell %i -assert-count 1
select @x_cell %co3 @y_cell %i -assert-count 1
# Check that z is (a & b) & (c & d)
select @x_cell %co3 @z_cell %i
select @x_cell %co3 @z_cell %i -assert-count 1
select @c_and_d_cells %co3 @z_cell %i -assert-count 1
design -reset
@ -168,7 +168,7 @@ select @c_cells @y_pre_cell %i -assert-count 1
select @x_cell %co3 @y_pre_cell %i -assert-count 1
# Check that z is (a & b) & (c & d)
select @x_cell %co3 @z_cell %i
select @x_cell %co3 @z_cell %i -assert-count 1
select @c_and_d_cells %co3 @z_cell %i -assert-count 1
design -reset
@ -524,7 +524,7 @@ select @c_cells @y_cell %i -assert-count 1
select @x_cell %co3 @y_cell %i -assert-count 1
# Check that z is (a + b) + (c + d)
select @x_cell %co3 @z_cell %i
select @x_cell %co3 @z_cell %i -assert-count 1
select @c_plus_d_cells %co3 @z_cell %i -assert-count 1
design -reset
@ -597,7 +597,7 @@ select @c_cells @y_pre_cell %i -assert-count 1
select @x_cell %co3 @y_pre_cell %i -assert-count 1
# Check that z is (a + b) + (c + d)
select @x_cell %co3 @z_cell %i
select @x_cell %co3 @z_cell %i -assert-count 1
select @c_plus_d_cells %co3 @z_cell %i -assert-count 1
design -reset