rtlil: Add wire deletion test

2026-08-22 14:17:27 +02:00 · 2024-01-29 11:25:54 +01:00
parent c035289383
commit ea3dc7c1b4
1 changed files with 8 additions and 0 deletions
@@ -0,0 +1,8 @@
+read_verilog <<EOF
+module top;
+  wire a;
+  wire b;
+  assign a = b;
+endmodule
+EOF
+delete w:a