luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 14:17:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fixed some missing "verilog_" in documentation

Browse Source
This commit is contained in:
Rodrigo Alejandro Melo
2019-12-13 10:17:05 -03:00
parent 9ab1feeaf1
commit e9dc2759c4
3 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
frontends/verilog/preproc.cc
+1 -1
View File
@@ -28,7 +28,7 @@
*
* Ad-hoc implementation of a Verilog preprocessor. The directives `define,
* `include, `ifdef, `ifndef, `else and `endif are handled here. All other
* directives are handled by the lexer (see lexer.l).
* directives are handled by the lexer (see verilog_lexer.l).
*
*/