mirror of https://github.com/YosysHQ/yosys.git
patch: fix patch mixins
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@ -22,6 +22,7 @@
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#include "kernel/newcelltypes.h"
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#include "kernel/newcelltypes.h"
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#include "kernel/binding.h"
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#include "kernel/binding.h"
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#include "kernel/sigtools.h"
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#include "kernel/sigtools.h"
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#include "kernel/unstable/patch.h"
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#include "kernel/threading.h"
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#include "kernel/threading.h"
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#include "frontends/verilog/verilog_frontend.h"
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#include "frontends/verilog/verilog_frontend.h"
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#include "frontends/verilog/preproc.h"
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#include "frontends/verilog/preproc.h"
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@ -5945,5 +5946,6 @@ std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
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#endif
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#endif
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template class CellAdderMixin<RTLIL::Module>;
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template class CellAdderMixin<RTLIL::Module>;
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template class CellAdderMixin<RTLIL::Patch>;
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YOSYS_NAMESPACE_END
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YOSYS_NAMESPACE_END
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