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Added module->design and cell->module, wire->module pointers

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This commit is contained in:
Clifford Wolf
2014-07-31 14:11:39 +02:00
parent 1cb25c05b3
commit e6d33513a5
15 changed files with 142 additions and 44 deletions
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manual/PRESENTATION_Prog/Makefile
+3 -3
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@@ -5,14 +5,14 @@ my_cmd.so: my_cmd.cc
../../yosys-config --exec --cxx --cxxflags --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
test0.log: my_cmd.so
../../yosys -l test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
mv test0.log_new test0.log
test1.log: my_cmd.so
../../yosys -l test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
mv test1.log_new test1.log
test2.log: my_cmd.so
../../yosys -l test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v
../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v
mv test2.log_new test2.log