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Merge remote-tracking branch 'upstream/main' into gw5a-dsp-inference

This commit is contained in:
Johan Olby 2026-07-16 13:23:59 +02:00
parent 7382f2bb19 45ea2b8d6c
commit e54c4fc737
No known key found for this signature in database
GPG Key ID: 099308365347DFA9
17 changed files with 176 additions and 41 deletions
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2
.github/workflows/codeql.yml vendored
View File

@ -34,7 +34,7 @@ jobs:
echo 'set(CMAKE_C_COMPILER clang CACHE STRING "")' >> Configuration.cmake
echo 'set(CMAKE_CXX_COMPILER clang++ CACHE STRING "")' >> Configuration.cmake
cmake -C Configuration.cmake -B build .
cmake -C Configuration.cmake -B build . -DYOSYS_WITHOUT_ABC=ON -DYOSYS_WITHOUT_SLANG=ON
cmake --build build -j6
- name: Perform CodeQL Analysis

2
.github/workflows/test-build.yml vendored
View File

@ -93,7 +93,7 @@ jobs:
shell: bash
run: |
rm -rf build
cmake -B build . -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ -DCMAKE_BUILD_TYPE=Release -DYOSYS_COMPILER_LAUNCHER=ccache
cmake -B build . -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ -DCMAKE_BUILD_TYPE=Release -DYOSYS_COMPILER_LAUNCHER=ccache -DYOSYS_USE_BUNDLED_LIBS=ON
cmake --build build -j$procs
ctest --test-dir build/tests/unit

2
CMakeLists.txt
View File

@ -57,6 +57,8 @@ option(YOSYS_WITHOUT_SLANG "Disable Slang integration" OFF)
option(YOSYS_WITHOUT_TCL "Disable Tcl integration" OFF)
option(YOSYS_WITH_PYTHON "Enable Python integration" OFF)
option(YOSYS_USE_BUNDLED_LIBS "Use bundled third-party libraries" OFF)
set(YOSYS_VERIFIC_DIR "" CACHE FILEPATH "Path to the Verific source code (empty to disable)")
set(YOSYS_VERIFIC_COMPONENTS "" CACHE STRING
"List of Verific components to link (empty for autodetect)")

4
frontends/CMakeLists.txt
View File

@ -6,6 +6,8 @@ add_subdirectory(json)
add_subdirectory(liberty)
add_subdirectory(rpc)
add_subdirectory(rtlil)
add_subdirectory(slang)
if (NOT YOSYS_WITHOUT_SLANG)
add_subdirectory(slang)
endif()
add_subdirectory(verific)
add_subdirectory(verilog)

1
frontends/slang/CMakeLists.txt
View File

@ -35,5 +35,4 @@ yosys_frontend(slang
${CMAKE_CURRENT_BINARY_DIR}
LIBRARIES
$<${YOSYS_ENABLE_SLANG}:slang::slang>
fmt::fmt
)

2
frontends/slang/lib

@ -1 +1 @@
Subproject commit 2caaaefa831a1d548a681268ccf3eea925ca1312
Subproject commit 3dddccd478618d68f8a5e160fb4b5783c4da35d4

1
kernel/version.cc.in
View File

@ -1,4 +1,5 @@
namespace Yosys {
const char *yosys_version_str = "@YOSYS_BUILD_INFO@";
const char *yosys_git_hash_str = "@YOSYS_CHECKOUT_INFO@";
const char *yosys_build_datetime_str = __DATE__ " " __TIME__;
}

1
kernel/yosys.h
View File

@ -82,6 +82,7 @@ extern std::set<std::string> yosys_input_files, yosys_output_files;
// from kernel/version_*.o (cc source generated from Makefile)
extern const char *yosys_version_str;
extern const char *yosys_git_hash_str;
extern const char *yosys_build_datetime_str;
const char* yosys_maybe_version();
// from passes/cmds/design.cc

61
libs/CMakeLists.txt
View File

@ -12,28 +12,49 @@ block()
include(FetchContent)
set(FETCHCONTENT_FULLY_DISCONNECTED ON)
option(FMT_INSTALL OFF)
FetchContent_Declare(
fmt
EXCLUDE_FROM_ALL
SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/fmt
)
FetchContent_MakeAvailable(fmt)
if(NOT YOSYS_USE_BUNDLED_LIBS)
find_package(fmt 12.2 QUIET)
endif()
if(fmt_FOUND)
set(SLANG_USE_SYSTEM_FMT ON)
else()
option(FMT_INSTALL OFF)
FetchContent_Declare(
fmt
EXCLUDE_FROM_ALL
SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/fmt
)
FetchContent_MakeAvailable(fmt)
endif()
FetchContent_Declare(
tomlplusplus
EXCLUDE_FROM_ALL
SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/tomlplusplus
)
FetchContent_MakeAvailable(tomlplusplus)
if(NOT YOSYS_USE_BUNDLED_LIBS)
find_package(tomlplusplus 3.4 QUIET)
endif()
if(tomlplusplus_FOUND)
set(SLANG_USE_SYSTEM_TOMLPLUSPLUS ON)
else()
FetchContent_Declare(
tomlplusplus
EXCLUDE_FROM_ALL
SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/tomlplusplus
)
FetchContent_MakeAvailable(tomlplusplus)
endif()
FetchContent_Declare(
boost_regex
EXCLUDE_FROM_ALL
SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/boost_regex
SOURCE_SUBDIR _no_build_
)
FetchContent_MakeAvailable(boost_regex)
if(NOT YOSYS_USE_BUNDLED_LIBS)
find_package(Boost 1.87.0 CONFIG QUIET)
endif()
if(Boost_FOUND)
set(SLANG_USE_SYSTEM_BOOST ON)
else()
FetchContent_Declare(
boost_regex
EXCLUDE_FROM_ALL
SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/boost_regex
SOURCE_SUBDIR _no_build_
)
FetchContent_MakeAvailable(boost_regex)
endif()
if (NOT YOSYS_WITHOUT_SLANG)
set(SLANG_USE_MIMALLOC OFF)

2
libs/slang

@ -1 +1 @@
Subproject commit 6175750969f17289695f94be5105f6006c82eb61
Subproject commit 8acc660a20b70de48ecec1c7471863e6f4b3ae6f

7
passes/techmap/dfflibmap.cc
View File

@ -272,17 +272,18 @@ static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type,
if (!parse_next_state(cell, ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol) || (has_enable && (cell_enable_pin.empty() || cell_enable_pol != enapol)))
continue;
bool cell_rstval = rstval;
if (has_reset && !cell_next_pol) {
// next_state is negated
// we later propagate this inversion to the output,
// which requires the negation of the reset value
rstval = !rstval;
cell_rstval = !rstval;
}
if (has_reset && rstval == false) {
if (has_reset && cell_rstval == false) {
if (!parse_pin(cell, ff->find("clear"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
continue;
}
if (has_reset && rstval == true) {
if (has_reset && cell_rstval == true) {
if (!parse_pin(cell, ff->find("preset"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
continue;
}

2
passes/techmap/liberty_cache.h
View File

@ -49,6 +49,8 @@ inline std::string convert_liberty_files_to_merged_scl(const std::vector<std::st
}
hash_input += dont_use_args;
// Include build datetime so caches from other builds are not reused
hash_input += yosys_build_datetime_str;
unsigned int hash = 0;
for (char c : hash_input)

26
techlibs/common/mul2dsp.v
View File

@ -68,6 +68,20 @@ module _80_mul (A, B, Y);
generate
if (0) begin end
// Normalize operand order (wider operand on A) to simplify asymmetric
// rules (DSP_A_MINWIDTH != DSP_B_MINWIDTH) below.
else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
\$mul #(
.A_SIGNED(B_SIGNED),
.B_SIGNED(A_SIGNED),
.A_WIDTH(B_WIDTH),
.B_WIDTH(A_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(B),
.B(A),
.Y(Y)
);
`ifdef DSP_A_MINWIDTH
else if (A_WIDTH < `DSP_A_MINWIDTH)
wire _TECHMAP_FAIL_ = 1;
@ -94,18 +108,6 @@ module _80_mul (A, B, Y);
.Y(Y)
);
`endif
else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
\$mul #(
.A_SIGNED(B_SIGNED),
.B_SIGNED(A_SIGNED),
.A_WIDTH(B_WIDTH),
.B_WIDTH(A_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(B),
.B(A),
.Y(Y)
);
else begin
wire [1023:0] _TECHMAP_DO_ = "proc; clean";

7
tests/liberty/scl_cache.ys Normal file
View File

@ -0,0 +1,7 @@
read_verilog small.v
synth -top small
abc -liberty normal.lib
logger -expect log "using cached merged SCL" 1
abc -liberty normal.lib
logger -check-expected

52
tests/techmap/dfflibmap_resetval_clobber.lib Normal file
View File

@ -0,0 +1,52 @@
library(test) {
cell (bad_dff) {
area : 1;
ff("IQ", "IQN") {
next_state : "!D"; // Look here
clocked_on : "CLK";
preset : "!RST"; // Look here
}
pin(D) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(RST) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
cell (good_dff) {
area : 1;
ff("IQ", "IQN") {
next_state : "D"; // Look here
clocked_on : "CLK";
clear : "RST"; // Look here
}
pin(D) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(RST) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
}

13
tests/techmap/dfflibmap_resetval_clobber.ys Normal file
View File

@ -0,0 +1,13 @@
read_verilog -icells <<EOT
module top(input C, D, R, output Q);
$_DFF_PP0_ ff (.C(C), .D(D), .R(R), .Q(Q));
endmodule
EOT
dfflibmap -liberty dfflibmap_resetval_clobber.lib top
read_liberty dfflibmap_resetval_clobber.lib
flatten -noscopeinfo
opt_clean
select -assert-count 1 t:* top %i
select -assert-count 1 t:$_DFF_PP0_ top %i

32
tests/techmap/mul2dsp_asymmetric.ys Normal file
View File

@ -0,0 +1,32 @@
# Test operand-order normalization: a 4x13 product with an asymmetric rule
# (A_MIN=10, B_MIN=4) fails in this order (A=4 < A_MIN) but maps to one DSP
# cell once the wide operand is normalized onto A.
read_verilog <<EOF
module top(a, b, y);
input signed [3:0] a;
input signed [12:0] b;
output signed [16:0] y;
assign y = a * b;
endmodule
EOF
read_verilog -lib <<EOF
module \$__MUL18X18 (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 18;
parameter B_WIDTH = 18;
parameter Y_WIDTH = 36;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
endmodule
EOF
hierarchy -top top
proc
techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=4 -D DSP_NAME=\$__MUL18X18
select -module top
select -assert-count 1 t:\$__MUL18X18