mirror of https://github.com/YosysHQ/yosys.git
rtlil: parameterize SigSpec::is_mostly_const
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@ -5605,13 +5605,13 @@ bool RTLIL::SigSpec::is_chunk() const
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return ++it == cs.end();
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}
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bool RTLIL::SigSpec::is_mostly_const() const
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bool RTLIL::SigSpec::is_mostly_const(double const_ratio_threshold) const
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{
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int constbits = 0;
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for (auto &chunk : chunks())
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if (chunk.width > 0 && chunk.wire == NULL)
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constbits += chunk.width;
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return (constbits > size()/2);
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return (constbits > size() * const_ratio_threshold);
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}
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bool RTLIL::SigSpec::known_driver() const
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@ -1684,7 +1684,9 @@ public:
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bool known_driver() const;
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bool is_mostly_const() const;
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// const_ratio_threshold is expected in [0.0, 1.0]
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// boundary is exclusive, returns true only if const bit ratio > const_ratio_threshold
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bool is_mostly_const(double const_ratio_threshold = 0.5) const;
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bool is_fully_const() const;
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bool is_fully_zero() const;
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bool is_fully_ones() const;
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