mirror of https://github.com/YosysHQ/yosys.git
share: use newcelltypes
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f4975f27ee
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e2e7e5ef6a
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@ -481,6 +481,15 @@ struct Categories {
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constexpr bool& operator[](size_t idx) {
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return data[idx];
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}
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constexpr void set_id(IdString type, bool val = true) {
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size_t idx = type.index_;
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if (idx >= MAX_CELLS)
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return; // TODO should be an assert but then it's not constexpr
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data[idx] = val;
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}
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constexpr void set(size_t idx, bool val = true) {
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data[idx] = val;
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}
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constexpr size_t size() const { return data.size(); }
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};
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Category empty {};
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@ -23,6 +23,7 @@
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#include "kernel/modtools.h"
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#include "kernel/utils.h"
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#include "kernel/macc.h"
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#include "kernel/newcelltypes.h"
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#include <iterator>
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USING_YOSYS_NAMESPACE
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@ -38,19 +39,18 @@ struct ShareWorkerConfig
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bool opt_force;
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bool opt_aggressive;
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bool opt_fast;
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pool<RTLIL::IdString> generic_uni_ops, generic_bin_ops, generic_cbin_ops, generic_other_ops;
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StaticCellTypes::Categories::Category generic_uni_ops, generic_bin_ops, generic_cbin_ops, generic_other_ops;
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};
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struct ShareWorker
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{
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const ShareWorkerConfig config;
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int limit;
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pool<RTLIL::IdString> generic_ops;
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StaticCellTypes::Categories::Category generic_ops;
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RTLIL::Design *design;
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RTLIL::Module *module;
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CellTypes fwd_ct, cone_ct;
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ModWalker modwalker;
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pool<RTLIL::Cell*> cells_to_remove;
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@ -75,7 +75,7 @@ struct ShareWorker
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queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end());
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for (auto &it : module->cells_)
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if (!fwd_ct.cell_known(it.second->type)) {
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if (!StaticCellTypes::Compat::internals_nomem_noff(it.second->type)) {
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pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second];
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queue_bits.insert(bits.begin(), bits.end());
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}
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@ -95,7 +95,7 @@ struct ShareWorker
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queue_bits.insert(bits.begin(), bits.end());
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visited_cells.insert(pbit.cell);
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}
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if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) {
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if (StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) {
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pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[pbit.cell];
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terminal_bits.insert(bits.begin(), bits.end());
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queue_bits.insert(bits.begin(), bits.end());
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@ -388,7 +388,7 @@ struct ShareWorker
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continue;
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}
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if (generic_ops.count(cell->type)) {
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if (generic_ops(cell->type)) {
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if (config.opt_aggressive)
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shareable_cells.insert(cell);
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continue;
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@ -412,7 +412,7 @@ struct ShareWorker
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return true;
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}
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if (config.generic_uni_ops.count(c1->type))
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if (config.generic_uni_ops(c1->type))
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{
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if (!config.opt_aggressive)
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{
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@ -429,7 +429,7 @@ struct ShareWorker
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return true;
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}
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if (config.generic_bin_ops.count(c1->type) || c1->type == ID($alu))
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if (config.generic_bin_ops(c1->type) || c1->type == ID($alu))
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{
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if (!config.opt_aggressive)
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{
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@ -449,7 +449,7 @@ struct ShareWorker
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return true;
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}
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if (config.generic_cbin_ops.count(c1->type))
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if (config.generic_cbin_ops(c1->type))
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{
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if (!config.opt_aggressive)
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{
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@ -511,7 +511,7 @@ struct ShareWorker
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{
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log_assert(c1->type == c2->type);
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if (config.generic_uni_ops.count(c1->type))
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if (config.generic_uni_ops(c1->type))
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{
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if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
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{
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@ -560,11 +560,11 @@ struct ShareWorker
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return supercell;
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}
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if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type) || c1->type == ID($alu))
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if (config.generic_bin_ops(c1->type) || config.generic_cbin_ops(c1->type) || c1->type == ID($alu))
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{
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bool modified_src_cells = false;
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if (config.generic_cbin_ops.count(c1->type))
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if (config.generic_cbin_ops(c1->type))
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{
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int score_unflipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int()) +
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max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int());
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@ -758,7 +758,7 @@ struct ShareWorker
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recursion_state.insert(cell);
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for (auto c : consumer_cells)
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if (fwd_ct.cell_known(c->type)) {
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if (StaticCellTypes::Compat::internals_nomem_noff(c->type)) {
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const pool<RTLIL::SigBit> &bits = find_forbidden_controls(c);
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forbidden_controls_cache[cell].insert(bits.begin(), bits.end());
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}
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@ -897,7 +897,7 @@ struct ShareWorker
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return activation_patterns_cache.at(cell);
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}
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for (auto &pbit : modwalker.signal_consumers[bit]) {
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log_assert(fwd_ct.cell_known(pbit.cell->type));
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log_assert(StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type));
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if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && (pbit.port == ID::A || pbit.port == ID::B))
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driven_data_muxes.insert(pbit.cell);
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else
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@ -1214,24 +1214,10 @@ struct ShareWorker
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ShareWorker(ShareWorkerConfig config, RTLIL::Design* design) :
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config(config), design(design), modwalker(design)
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{
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generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end());
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generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end());
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generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end());
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generic_ops.insert(config.generic_other_ops.begin(), config.generic_other_ops.end());
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fwd_ct.setup_internals();
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cone_ct.setup_internals();
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cone_ct.cell_types.erase(ID($mul));
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cone_ct.cell_types.erase(ID($mod));
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cone_ct.cell_types.erase(ID($div));
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cone_ct.cell_types.erase(ID($modfloor));
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cone_ct.cell_types.erase(ID($divfloor));
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cone_ct.cell_types.erase(ID($pow));
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cone_ct.cell_types.erase(ID($shl));
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cone_ct.cell_types.erase(ID($shr));
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cone_ct.cell_types.erase(ID($sshl));
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cone_ct.cell_types.erase(ID($sshr));
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generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_uni_ops);
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generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_bin_ops);
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generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_cbin_ops);
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generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_other_ops);
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}
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void operator()(RTLIL::Module *module) {
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@ -1561,45 +1547,45 @@ struct SharePass : public Pass {
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config.opt_aggressive = false;
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config.opt_fast = false;
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config.generic_uni_ops.insert(ID($not));
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// config.generic_uni_ops.insert(ID($pos));
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config.generic_uni_ops.insert(ID($neg));
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config.generic_uni_ops.set_id(ID($not));
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// config.generic_uni_ops.set_id(ID($pos));
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config.generic_uni_ops.set_id(ID($neg));
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config.generic_cbin_ops.insert(ID($and));
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config.generic_cbin_ops.insert(ID($or));
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config.generic_cbin_ops.insert(ID($xor));
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config.generic_cbin_ops.insert(ID($xnor));
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config.generic_cbin_ops.set_id(ID($and));
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config.generic_cbin_ops.set_id(ID($or));
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config.generic_cbin_ops.set_id(ID($xor));
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config.generic_cbin_ops.set_id(ID($xnor));
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config.generic_bin_ops.insert(ID($shl));
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config.generic_bin_ops.insert(ID($shr));
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config.generic_bin_ops.insert(ID($sshl));
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config.generic_bin_ops.insert(ID($sshr));
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config.generic_bin_ops.set_id(ID($shl));
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config.generic_bin_ops.set_id(ID($shr));
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config.generic_bin_ops.set_id(ID($sshl));
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config.generic_bin_ops.set_id(ID($sshr));
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config.generic_bin_ops.insert(ID($lt));
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config.generic_bin_ops.insert(ID($le));
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config.generic_bin_ops.insert(ID($eq));
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config.generic_bin_ops.insert(ID($ne));
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config.generic_bin_ops.insert(ID($eqx));
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config.generic_bin_ops.insert(ID($nex));
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config.generic_bin_ops.insert(ID($ge));
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config.generic_bin_ops.insert(ID($gt));
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config.generic_bin_ops.set_id(ID($lt));
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config.generic_bin_ops.set_id(ID($le));
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config.generic_bin_ops.set_id(ID($eq));
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config.generic_bin_ops.set_id(ID($ne));
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config.generic_bin_ops.set_id(ID($eqx));
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config.generic_bin_ops.set_id(ID($nex));
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config.generic_bin_ops.set_id(ID($ge));
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config.generic_bin_ops.set_id(ID($gt));
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config.generic_cbin_ops.insert(ID($add));
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config.generic_cbin_ops.insert(ID($mul));
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config.generic_cbin_ops.set_id(ID($add));
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config.generic_cbin_ops.set_id(ID($mul));
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config.generic_bin_ops.insert(ID($sub));
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config.generic_bin_ops.insert(ID($div));
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config.generic_bin_ops.insert(ID($mod));
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config.generic_bin_ops.insert(ID($divfloor));
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config.generic_bin_ops.insert(ID($modfloor));
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// config.generic_bin_ops.insert(ID($pow));
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config.generic_bin_ops.set_id(ID($sub));
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config.generic_bin_ops.set_id(ID($div));
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config.generic_bin_ops.set_id(ID($mod));
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config.generic_bin_ops.set_id(ID($divfloor));
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config.generic_bin_ops.set_id(ID($modfloor));
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// config.generic_bin_ops.set_id(ID($pow));
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config.generic_uni_ops.insert(ID($logic_not));
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config.generic_cbin_ops.insert(ID($logic_and));
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config.generic_cbin_ops.insert(ID($logic_or));
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config.generic_uni_ops.set_id(ID($logic_not));
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config.generic_cbin_ops.set_id(ID($logic_and));
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config.generic_cbin_ops.set_id(ID($logic_or));
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config.generic_other_ops.insert(ID($alu));
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config.generic_other_ops.insert(ID($macc));
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config.generic_other_ops.set_id(ID($alu));
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config.generic_other_ops.set_id(ID($macc));
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log_header(design, "Executing SHARE pass (SAT-based resource sharing).\n");
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