luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fix for VHDL default library path handling

This commit is contained in:
Dhaval Chaudhari 2026-01-05 23:32:23 +05:30
parent 0f279eef41
commit e0ce4b42f6
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
frontends/verific/verific.cc
View File

@ -3692,15 +3692,15 @@ struct VerificPass : public Pass {
break;
}
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") {
for (argidx++; argidx < GetSize(args); argidx++) {
#ifdef VERIFIC_VHDL_SUPPORT
if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") {
for (argidx++; argidx < GetSize(args); argidx++)
vhdl_file::SetDefaultLibraryPath(args[argidx].c_str());
#endif
}
goto check_error;
}
#endif
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
{
unsigned verilog_mode = veri_file::UNDEFINED;