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Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup

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Optimise write_xaiger
This commit is contained in:
Eddie Hung
2019-12-19 12:24:03 -05:00
committed by GitHub
parent d406f2ffd7 91467938c4
commit df626ee7ab
4 changed files with 39 additions and 21 deletions
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techlibs/xilinx/synth_xilinx.cc
+5
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@@ -540,6 +540,11 @@ struct SynthXilinxPass : public ScriptPass
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
run("wbflip @abc9_boxes");
run("techmap -autoproc @abc9_boxes");
run("aigmap @abc9_boxes");
run("wbflip @abc9_boxes");
run("read_verilog -icells -lib +/xilinx/abc9_model.v");
std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);