mirror of https://github.com/YosysHQ/yosys.git
Avoid scanning entire module if there are no wires to remove
It's pretty common for `opt_clean` to find no wires to remove. In that case, there is no point scanning the entire design, which can be significantly expensive for huge designs.
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125609105d
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@ -2990,6 +2990,8 @@ void RTLIL::Module::add(RTLIL::Binding *binding)
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void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
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void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
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{
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{
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log_assert(refcount_wires_ == 0);
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log_assert(refcount_wires_ == 0);
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if (wires.empty())
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return;
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struct DeleteWireWorker
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struct DeleteWireWorker
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{
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{
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