mirror of https://github.com/YosysHQ/yosys.git
dfflibmap: refactor
This commit is contained in:
Emil J. Tywoniak
parent
d4239cfc60
commit
dc70d58b76
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@ -20,7 +20,9 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/gzip.h"
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#include "kernel/ff.h"
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#include "libparse.h"
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#include <cstddef>
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#include <string.h>
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#include <errno.h>
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@ -33,6 +35,104 @@ struct cell_mapping {
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};
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static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
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static void strip_chars(std::string &s, const char *chars)
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{
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for (size_t pos = s.find_first_of(chars); pos != std::string::npos; pos = s.find_first_of(chars))
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s.erase(pos, 1);
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}
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static bool is_dont_use(const LibertyAst *cell, std::vector<std::string> &dont_use_cells)
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{
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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return true;
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for (auto &pat : dont_use_cells)
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if (patmatch(pat.c_str(), cell->args[0].c_str()))
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return true;
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return false;
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}
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// State for evaluating a candidate library cell
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struct CellMatch {
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std::map<std::string, char> ports;
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int num_pins = 0;
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bool has_noninv_output = false;
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enum ScanResult {
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REJECT, // cell has unconnected inputs
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NO_OUTPUT, // cell is valid but has no Q/QN output
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OK // cell is valid with output found
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};
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// Scan cell pins to count them, check inputs, and identify Q/QN outputs.
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ScanResult scan_outputs(const LibertyAst *cell, const LibertyAst *ff, bool cell_next_pol)
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{
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bool found_output = false;
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for (auto pin : cell->children) {
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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const LibertyAst *dir = pin->find("direction");
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if (dir == nullptr || dir->value == "internal")
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continue;
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num_pins++;
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if (dir->value == "input" && ports.count(pin->args[0]) == 0)
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return REJECT;
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const LibertyAst *func = pin->find("function");
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if (dir->value == "output" && func != nullptr) {
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std::string value = func->value;
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strip_chars(value, "\" \t");
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// next_state negation propagated to output
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if (value == ff->args[0]) {
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ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q';
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if (cell_next_pol) has_noninv_output = true;
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found_output = true;
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} else if (value == ff->args[1]) {
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ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q';
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if (!cell_next_pol) has_noninv_output = true;
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found_output = true;
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}
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}
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if (ports.count(pin->args[0]) == 0)
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ports[pin->args[0]] = 0;
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}
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return found_output ? OK : NO_OUTPUT;
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}
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};
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// State for tracking the best matching library cell found so far
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struct BestCell : CellMatch {
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const LibertyAst *cell = nullptr;
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double area = 0;
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// Update best cell if candidate is better (fewer pins, has noninv output, smaller area)
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void update(const LibertyAst *candidate, CellMatch &match)
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{
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if (cell != nullptr && (match.num_pins > num_pins || (has_noninv_output && !match.has_noninv_output)))
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return;
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double candidate_area = 0;
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const LibertyAst *ar = candidate->find("area");
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if (ar != nullptr && !ar->value.empty())
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candidate_area = atof(ar->value.c_str());
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if (cell != nullptr && match.num_pins == num_pins && candidate_area > area)
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return;
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cell = candidate;
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num_pins = match.num_pins;
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area = candidate_area;
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has_noninv_output = match.has_noninv_output;
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ports.swap(match.ports);
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}
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void record_mapping(IdString cell_type)
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{
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if (cell != nullptr) {
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log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
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cell->args[0].c_str(), has_noninv_output ? "non" : "", num_pins, area, cell_type.c_str());
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cell_mappings[cell_type].cell_name = RTLIL::escape_id(cell->args[0]);
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cell_mappings[cell_type].ports = ports;
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}
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}
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};
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static void logmap(IdString dff)
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{
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if (cell_mappings.count(dff) == 0) {
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@ -53,33 +153,24 @@ static void logmap(IdString dff)
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}
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}
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static bool is_supported_ff(const FfTypeData &ff)
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{
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// only support fine cells with clk, no aload/srst/gclk
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if (!ff.is_fine || !ff.has_clk || ff.has_aload || ff.has_srst || ff.has_gclk)
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return false;
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// no combined enable with reset/sr
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if (ff.has_ce && (ff.has_arst || ff.has_sr))
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return false;
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return true;
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}
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static void logmap_all()
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{
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logmap(ID($_DFF_N_));
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logmap(ID($_DFF_P_));
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logmap(ID($_DFF_NN0_));
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logmap(ID($_DFF_NN1_));
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logmap(ID($_DFF_NP0_));
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logmap(ID($_DFF_NP1_));
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logmap(ID($_DFF_PN0_));
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logmap(ID($_DFF_PN1_));
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logmap(ID($_DFF_PP0_));
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logmap(ID($_DFF_PP1_));
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logmap(ID($_DFFE_NN_));
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logmap(ID($_DFFE_NP_));
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logmap(ID($_DFFE_PN_));
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logmap(ID($_DFFE_PP_));
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logmap(ID($_DFFSR_NNN_));
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logmap(ID($_DFFSR_NNP_));
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logmap(ID($_DFFSR_NPN_));
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logmap(ID($_DFFSR_NPP_));
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logmap(ID($_DFFSR_PNN_));
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logmap(ID($_DFFSR_PNP_));
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logmap(ID($_DFFSR_PPN_));
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logmap(ID($_DFFSR_PPP_));
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for (auto type : RTLIL::builtin_ff_cell_types()) {
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FfTypeData ff(type);
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if (is_supported_ff(ff))
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logmap(type);
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}
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}
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static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std::string &data_name, bool &data_not_inverted, std::string &enable_name, bool &enable_not_inverted)
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@ -92,8 +183,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std
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auto expr = attr->value;
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auto cell_name = cell->args[0];
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for (size_t pos = expr.find_first_of("\"\t"); pos != std::string::npos; pos = expr.find_first_of("\"\t"))
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expr.erase(pos, 1);
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strip_chars(expr, "\"\t");
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// if this isn't an enable flop, the next_state variable is usually just the input pin name.
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if (expr[expr.size()-1] == '\'') {
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@ -201,9 +291,7 @@ static bool parse_pin(const LibertyAst *cell, const LibertyAst *attr, std::strin
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return false;
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std::string value = attr->value;
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for (size_t pos = value.find_first_of("\" \t()"); pos != std::string::npos; pos = value.find_first_of("\" \t()"))
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value.erase(pos, 1);
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strip_chars(value, "\" \t()");
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if (value[value.size()-1] == '\'') {
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pin_name = value.substr(0, value.size()-1);
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@ -234,264 +322,98 @@ static bool parse_pin(const LibertyAst *cell, const LibertyAst *attr, std::strin
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return false;
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}
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static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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{
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const LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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bool best_cell_noninv = false;
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double best_cell_area = 0;
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struct DffFinder {
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std::vector<const LibertyAst *> &cells;
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std::vector<std::string> &dont_use_cells;
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for (auto cell : cells)
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void find(IdString cell_type, const FfTypeData &ff)
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{
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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BestCell best;
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bool dont_use = false;
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for (std::string &dont_use_cell : dont_use_cells)
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{
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if (patmatch(dont_use_cell.c_str(), cell->args[0].c_str()))
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{
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dont_use = true;
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break;
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}
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}
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if (dont_use)
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continue;
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for (auto cell : cells) {
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if (is_dont_use(cell, dont_use_cells))
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continue;
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const LibertyAst *cell_ff = cell->find("ff");
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if (cell_ff == nullptr)
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continue;
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const LibertyAst *ff = cell->find("ff");
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if (ff == nullptr)
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continue;
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std::string cell_clk_pin, cell_rst_pin, cell_next_pin, cell_enable_pin;
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bool cell_clk_pol, cell_rst_pol, cell_next_pol, cell_enable_pol;
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std::string cell_clk_pin, cell_rst_pin, cell_next_pin, cell_enable_pin;
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bool cell_clk_pol, cell_rst_pol, cell_next_pol, cell_enable_pol;
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if (!parse_pin(cell, cell_ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != ff.pol_clk)
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continue;
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if (!parse_next_state(cell, cell_ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol) || (ff.has_ce && (cell_enable_pin.empty() || cell_enable_pol != ff.pol_ce)))
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continue;
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if (!parse_pin(cell, ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != clkpol)
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continue;
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if (!parse_next_state(cell, ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol) || (has_enable && (cell_enable_pin.empty() || cell_enable_pol != enapol)))
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continue;
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if (has_reset && !cell_next_pol) {
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// next_state is negated
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// we later propagate this inversion to the output,
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// next_state is negated, we later propagate this inversion to the output,
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// which requires the negation of the reset value
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rstval = !rstval;
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}
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if (has_reset && rstval == false) {
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if (!parse_pin(cell, ff->find("clear"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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}
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if (has_reset && rstval == true) {
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if (!parse_pin(cell, ff->find("preset"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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}
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std::map<std::string, char> this_cell_ports;
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this_cell_ports[cell_clk_pin] = 'C';
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if (has_reset)
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this_cell_ports[cell_rst_pin] = 'R';
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if (has_enable)
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this_cell_ports[cell_enable_pin] = 'E';
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this_cell_ports[cell_next_pin] = 'D';
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double area = 0;
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const LibertyAst *ar = cell->find("area");
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if (ar != nullptr && !ar->value.empty())
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area = atof(ar->value.c_str());
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int num_pins = 0;
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bool found_output = false;
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bool found_noninv_output = false;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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const LibertyAst *dir = pin->find("direction");
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if (dir == nullptr || dir->value == "internal")
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continue;
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num_pins++;
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if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
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goto continue_cell_loop;
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const LibertyAst *func = pin->find("function");
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if (dir->value == "output" && func != nullptr) {
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std::string value = func->value;
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if (value == ff->args[0]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q';
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if (cell_next_pol)
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found_noninv_output = true;
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found_output = true;
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} else
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if (value == ff->args[1]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q';
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if (!cell_next_pol)
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found_noninv_output = true;
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found_output = true;
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}
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if (ff.has_arst) {
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bool rstval = ff.val_arst[0] == State::S1;
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if (!cell_next_pol)
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rstval = !rstval;
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if (!parse_pin(cell, cell_ff->find(rstval ? "preset" : "clear"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != ff.pol_arst)
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continue;
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}
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if (this_cell_ports.count(pin->args[0]) == 0)
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this_cell_ports[pin->args[0]] = 0;
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CellMatch match;
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match.ports[cell_clk_pin] = 'C';
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if (ff.has_arst) match.ports[cell_rst_pin] = 'R';
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if (ff.has_ce) match.ports[cell_enable_pin] = 'E';
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match.ports[cell_next_pin] = 'D';
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if (match.scan_outputs(cell, cell_ff, cell_next_pol) != CellMatch::OK)
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continue;
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best.update(cell, match);
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}
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if (!found_output || (best_cell != nullptr && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output))))
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continue;
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if (best_cell != nullptr && num_pins == best_cell_pins && area > best_cell_area)
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continue;
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best_cell = cell;
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best_cell_pins = num_pins;
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best_cell_area = area;
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best_cell_noninv = found_noninv_output;
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best_cell_ports.swap(this_cell_ports);
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continue_cell_loop:;
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best.record_mapping(cell_type);
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}
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if (best_cell != nullptr) {
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log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
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best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
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cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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}
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static void find_cell_sr(std::vector<const LibertyAst *> cells, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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{
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const LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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bool best_cell_noninv = false;
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double best_cell_area = 0;
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log_assert(!enapol && "set/reset cell with enable is unimplemented due to lack of cells for testing");
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for (auto cell : cells)
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void find_sr(IdString cell_type, const FfTypeData &ff)
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{
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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BestCell best;
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bool dont_use = false;
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for (std::string &dont_use_cell : dont_use_cells)
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{
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if (patmatch(dont_use_cell.c_str(), cell->args[0].c_str()))
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{
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dont_use = true;
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break;
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}
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}
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if (dont_use)
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continue;
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log_assert(!ff.has_ce && "set/reset cell with enable is unimplemented due to lack of cells for testing");
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const LibertyAst *ff = cell->find("ff");
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if (ff == nullptr)
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continue;
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for (auto cell : cells) {
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if (is_dont_use(cell, dont_use_cells))
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continue;
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const LibertyAst *cell_ff = cell->find("ff");
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if (cell_ff == nullptr)
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continue;
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std::string cell_clk_pin, cell_set_pin, cell_clr_pin, cell_next_pin, cell_enable_pin;
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bool cell_clk_pol, cell_set_pol, cell_clr_pol, cell_next_pol, cell_enable_pol;
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std::string cell_clk_pin, cell_set_pin, cell_clr_pin, cell_next_pin, cell_enable_pin;
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bool cell_clk_pol, cell_set_pol, cell_clr_pol, cell_next_pol, cell_enable_pol;
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if (!parse_pin(cell, ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != clkpol)
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continue;
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if (!parse_next_state(cell, ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol))
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continue;
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if (!parse_pin(cell, ff->find("preset"), cell_set_pin, cell_set_pol))
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continue;
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if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol))
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continue;
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if (!cell_next_pol) {
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// next_state is negated
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// we later propagate this inversion to the output,
|
||||
if (!parse_pin(cell, cell_ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != ff.pol_clk)
|
||||
continue;
|
||||
if (!parse_next_state(cell, cell_ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol))
|
||||
continue;
|
||||
if (!parse_pin(cell, cell_ff->find("preset"), cell_set_pin, cell_set_pol) ||
|
||||
!parse_pin(cell, cell_ff->find("clear"), cell_clr_pin, cell_clr_pol))
|
||||
continue;
|
||||
// next_state is negated, we later propagate this inversion to the output,
|
||||
// which requires the swap of set and reset
|
||||
std::swap(cell_set_pin, cell_clr_pin);
|
||||
std::swap(cell_set_pol, cell_clr_pol);
|
||||
}
|
||||
if (cell_set_pol != setpol)
|
||||
continue;
|
||||
if (cell_clr_pol != clrpol)
|
||||
continue;
|
||||
|
||||
std::map<std::string, char> this_cell_ports;
|
||||
this_cell_ports[cell_clk_pin] = 'C';
|
||||
this_cell_ports[cell_set_pin] = 'S';
|
||||
this_cell_ports[cell_clr_pin] = 'R';
|
||||
if (has_enable)
|
||||
this_cell_ports[cell_enable_pin] = 'E';
|
||||
this_cell_ports[cell_next_pin] = 'D';
|
||||
|
||||
double area = 0;
|
||||
const LibertyAst *ar = cell->find("area");
|
||||
if (ar != nullptr && !ar->value.empty())
|
||||
area = atof(ar->value.c_str());
|
||||
|
||||
int num_pins = 0;
|
||||
bool found_output = false;
|
||||
bool found_noninv_output = false;
|
||||
for (auto pin : cell->children)
|
||||
{
|
||||
if (pin->id != "pin" || pin->args.size() != 1)
|
||||
continue;
|
||||
|
||||
const LibertyAst *dir = pin->find("direction");
|
||||
if (dir == nullptr || dir->value == "internal")
|
||||
continue;
|
||||
num_pins++;
|
||||
|
||||
if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
|
||||
goto continue_cell_loop;
|
||||
|
||||
const LibertyAst *func = pin->find("function");
|
||||
if (dir->value == "output" && func != nullptr) {
|
||||
std::string value = func->value;
|
||||
for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
|
||||
value.erase(pos, 1);
|
||||
if (value == ff->args[0]) {
|
||||
// next_state negation propagated to output
|
||||
this_cell_ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q';
|
||||
if (cell_next_pol)
|
||||
found_noninv_output = true;
|
||||
found_output = true;
|
||||
} else
|
||||
if (value == ff->args[1]) {
|
||||
// next_state negation propagated to output
|
||||
this_cell_ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q';
|
||||
if (!cell_next_pol)
|
||||
found_noninv_output = true;
|
||||
found_output = true;
|
||||
}
|
||||
if (!cell_next_pol) {
|
||||
std::swap(cell_set_pin, cell_clr_pin);
|
||||
std::swap(cell_set_pol, cell_clr_pol);
|
||||
}
|
||||
if (cell_set_pol != ff.pol_set || cell_clr_pol != ff.pol_clr)
|
||||
continue;
|
||||
|
||||
if (this_cell_ports.count(pin->args[0]) == 0)
|
||||
this_cell_ports[pin->args[0]] = 0;
|
||||
CellMatch match;
|
||||
match.ports[cell_clk_pin] = 'C';
|
||||
match.ports[cell_set_pin] = 'S';
|
||||
match.ports[cell_clr_pin] = 'R';
|
||||
if (ff.has_ce) match.ports[cell_enable_pin] = 'E';
|
||||
match.ports[cell_next_pin] = 'D';
|
||||
|
||||
if (match.scan_outputs(cell, cell_ff, cell_next_pol) != CellMatch::OK)
|
||||
continue;
|
||||
best.update(cell, match);
|
||||
}
|
||||
|
||||
if (!found_output || (best_cell != nullptr && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output))))
|
||||
continue;
|
||||
|
||||
if (best_cell != nullptr && num_pins == best_cell_pins && area > best_cell_area)
|
||||
continue;
|
||||
|
||||
best_cell = cell;
|
||||
best_cell_pins = num_pins;
|
||||
best_cell_area = area;
|
||||
best_cell_noninv = found_noninv_output;
|
||||
best_cell_ports.swap(this_cell_ports);
|
||||
continue_cell_loop:;
|
||||
best.record_mapping(cell_type);
|
||||
}
|
||||
|
||||
if (best_cell != nullptr) {
|
||||
log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
|
||||
best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
|
||||
cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
|
||||
cell_mappings[cell_type].ports = best_cell_ports;
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
|
||||
{
|
||||
|
|
@ -533,8 +455,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
|
|||
RTLIL::SigSpec sig;
|
||||
if ('A' <= port.second && port.second <= 'Z') {
|
||||
sig = cell_connections[std::string("\\") + port.second];
|
||||
} else
|
||||
if (port.second == 'q') {
|
||||
} else if (port.second == 'q') {
|
||||
RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
|
||||
sig = module->addWire(NEW_ID, GetSize(old_sig));
|
||||
if (has_q && has_qn) {
|
||||
|
|
@ -545,18 +466,16 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
|
|||
} else {
|
||||
module->addNotGate(NEW_ID, sig, old_sig);
|
||||
}
|
||||
} else
|
||||
if ('a' <= port.second && port.second <= 'z') {
|
||||
} else if ('a' <= port.second && port.second <= 'z') {
|
||||
sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
|
||||
sig = module->NotGate(NEW_ID, sig);
|
||||
} else
|
||||
if (port.second == '0' || port.second == '1') {
|
||||
} else if (port.second == '0' || port.second == '1') {
|
||||
sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
|
||||
} else
|
||||
if (port.second == 0) {
|
||||
} else if (port.second == 0) {
|
||||
sig = module->addWire(NEW_ID);
|
||||
} else
|
||||
} else {
|
||||
log_abort();
|
||||
}
|
||||
new_cell->setPort("\\" + port.first, sig);
|
||||
}
|
||||
|
||||
|
|
@ -639,14 +558,7 @@ struct DfflibmapPass : public Pass {
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
int modes = 0;
|
||||
if (prepare_mode)
|
||||
modes++;
|
||||
if (map_only_mode)
|
||||
modes++;
|
||||
if (info_mode)
|
||||
modes++;
|
||||
if (modes > 1)
|
||||
if (prepare_mode + map_only_mode + info_mode > 1)
|
||||
log_cmd_error("Only one of -prepare, -map-only, or -info options should be given!\n");
|
||||
|
||||
if (liberty_files.empty())
|
||||
|
|
@ -660,31 +572,16 @@ struct DfflibmapPass : public Pass {
|
|||
delete f;
|
||||
}
|
||||
|
||||
find_cell(merged.cells, ID($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
|
||||
|
||||
find_cell(merged.cells, ID($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
|
||||
|
||||
find_cell(merged.cells, ID($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
|
||||
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
|
||||
DffFinder finder{merged.cells, dont_use_cells};
|
||||
for (auto type : RTLIL::builtin_ff_cell_types()) {
|
||||
FfTypeData ff(type);
|
||||
if (!is_supported_ff(ff))
|
||||
continue;
|
||||
if (ff.has_sr)
|
||||
finder.find_sr(type, ff);
|
||||
else
|
||||
finder.find(type, ff);
|
||||
}
|
||||
|
||||
log(" final dff cell mappings:\n");
|
||||
logmap_all();
|
||||
|
|
|
|||
Loading…
Reference in New Issue