Add test from #1144, and try reading without '-specify' flag

2026-08-22 14:17:27 +02:00 · 2019-06-28 10:12:48 -07:00
parent af74409749
commit dc677c791d
2 changed files with 16 additions and 0 deletions
@@ -54,3 +54,5 @@ equiv_struct
 equiv_induct -seq 5
 equiv_status -assert
 design -reset
+
+read_verilog specify.v