Allow $size and $bits in verilog mode, actually check test case

2026-08-22 06:07:26 +02:00 · 2017-09-29 11:56:43 +02:00
parent 637a02eb5c
commit dbfd8460a9
3 changed files with 3 additions and 1 deletions
@@ -0,0 +1,2 @@
+read_verilog -sv sizebits.sv
+prep; sat -verify -prove-asserts