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Changed more code to the new RTLIL::Wire constructors

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This commit is contained in:
Clifford Wolf
2014-07-26 21:30:38 +02:00
parent 946ddff9ce
commit d68c993ed2
8 changed files with 52 additions and 81 deletions
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passes/techmap/iopadmap.cc
+2 -7
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@@ -164,13 +164,8 @@ struct IopadmapPass : public Pass {
log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
RTLIL::Wire *new_wire = NULL;
if (!portname2.empty()) {
new_wire = new RTLIL::Wire;
*new_wire = *wire;
wire->name = NEW_ID;
module->wires[wire->name] = wire;
module->wires[new_wire->name] = new_wire;
}
if (!portname2.empty())
new_wire = module->addWire(NEW_ID, wire);
if (flag_bits)
{