mirror of https://github.com/YosysHQ/yosys.git
techmap: decode derived_name in the map pool, not the target design
derived_name and the template's marker wire are interned in map->twines; decoding them with design->twines read an out-of-range/foreign pool slot (garbage, or a crash once pool sizes diverge) in the _TECHMAP_FAIL_ log. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
parent
3c0056a4c1
commit
d5c1875055
|
|
@ -798,7 +798,7 @@ struct TechmapWorker
|
|||
RTLIL::SigSpec value = elem.value;
|
||||
if (value.is_fully_const() && value.as_bool()) {
|
||||
log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
|
||||
design->twines.unescaped_str(derived_name).data(), design->twines.unescaped_str(elem.wire->name.ref()).data(), log_signal(value));
|
||||
map->twines.unescaped_str(derived_name).data(), map->twines.unescaped_str(elem.wire->name.ref()).data(), log_signal(value));
|
||||
techmap_do_cache[tpl] = false;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue