mirror of https://github.com/YosysHQ/yosys.git
added SIMLIB_VERILATOR_COMPAT
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@ -31,6 +31,14 @@
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*/
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// If using Verilator, define SIMLIB_VERILATOR_COMPAT
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`ifdef SIMLIB_VERILATOR_COMPAT
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/* verilator lint_save */
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/* verilator lint_off DEFOVERRIDE */
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`define SIMLIB_NOCONNECT
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/* verilator lint_restore */
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`endif
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// --------------------------------------------------------
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// --------------------------------------------------------
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//* ver 2
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//* ver 2
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//* title Bit-wise inverter
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//* title Bit-wise inverter
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