mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #6038 from YosysHQ/emil/dfflibmap-fix-resetval
dfflibmap: fix resetval clobber
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commit
d4f39588a7
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@ -272,17 +272,18 @@ static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type,
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if (!parse_next_state(cell, ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol) || (has_enable && (cell_enable_pin.empty() || cell_enable_pol != enapol)))
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if (!parse_next_state(cell, ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol) || (has_enable && (cell_enable_pin.empty() || cell_enable_pol != enapol)))
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continue;
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continue;
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bool cell_rstval = rstval;
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if (has_reset && !cell_next_pol) {
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if (has_reset && !cell_next_pol) {
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// next_state is negated
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// next_state is negated
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// we later propagate this inversion to the output,
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// we later propagate this inversion to the output,
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// which requires the negation of the reset value
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// which requires the negation of the reset value
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rstval = !rstval;
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cell_rstval = !rstval;
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}
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}
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if (has_reset && rstval == false) {
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if (has_reset && cell_rstval == false) {
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if (!parse_pin(cell, ff->find("clear"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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if (!parse_pin(cell, ff->find("clear"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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continue;
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}
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}
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if (has_reset && rstval == true) {
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if (has_reset && cell_rstval == true) {
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if (!parse_pin(cell, ff->find("preset"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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if (!parse_pin(cell, ff->find("preset"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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continue;
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}
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}
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@ -0,0 +1,52 @@
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library(test) {
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cell (bad_dff) {
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area : 1;
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ff("IQ", "IQN") {
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next_state : "!D"; // Look here
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clocked_on : "CLK";
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preset : "!RST"; // Look here
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(RST) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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cell (good_dff) {
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area : 1;
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ff("IQ", "IQN") {
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next_state : "D"; // Look here
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clocked_on : "CLK";
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clear : "RST"; // Look here
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(RST) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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}
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@ -0,0 +1,13 @@
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read_verilog -icells <<EOT
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module top(input C, D, R, output Q);
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$_DFF_PP0_ ff (.C(C), .D(D), .R(R), .Q(Q));
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endmodule
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EOT
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dfflibmap -liberty dfflibmap_resetval_clobber.lib top
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read_liberty dfflibmap_resetval_clobber.lib
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flatten -noscopeinfo
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opt_clean
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select -assert-count 1 t:* top %i
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select -assert-count 1 t:$_DFF_PP0_ top %i
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