luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 14:17:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

Revert "Refactor full_selection"

Browse Source
This commit is contained in:
Miodrag Milanović
2025-04-07 12:11:55 +02:00
committed by GitHub
parent 98d4355b82
commit d49364d96f
38 changed files with 270 additions and 707 deletions
Download Patch File Download Diff File Expand all files Collapse all files
passes/cmds/add.cc
+1 -1
View File
@@ -102,7 +102,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
RTLIL::Module *mod = design->module(cell->type);
if (mod == nullptr)
continue;
if (!mod->is_selected_whole())
if (!design->selected_whole_module(mod->name))
continue;
if (mod->get_blackbox_attribute())
continue;