mirror of https://github.com/YosysHQ/yosys.git
read_liberty: fix for msvc
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5858ad2648
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d4239cfc60
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@ -20,6 +20,7 @@
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#include "passes/techmap/libparse.h"
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <array>
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YOSYS_NAMESPACE_BEGIN
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@ -225,7 +226,8 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
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if (child->id == "preset")
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preset_sig = parse_func_expr(module, child->value.c_str());
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for (auto& [id, var] : {pair{"clear_preset_var1", &clear_preset_var1}, {"clear_preset_var2", &clear_preset_var2}})
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using SillyMsvcType = std::tuple<const char*, std::optional<char>*>;
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for (auto& [id, var] : std::array<SillyMsvcType, 2>{SillyMsvcType{"clear_preset_var1", &clear_preset_var1}, {"clear_preset_var2", &clear_preset_var2}})
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if (child->id == id) {
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if (child->value.size() != 1)
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log_error("Unexpected length of clear_preset_var* value %s in FF cell %s\n", child->value, name);
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@ -266,7 +268,8 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
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}
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}
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for (auto& [out_sig, cp_var, neg] : {tuple{iq_sig, clear_preset_var1, false}, {iqn_sig, clear_preset_var2, true}}) {
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using SillyMsvcType = std::tuple<SigSpec&, std::optional<char>&, bool>;
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for (auto& [out_sig, cp_var, neg] : std::array<SillyMsvcType, 2>{SillyMsvcType{iq_sig, clear_preset_var1, false}, {iqn_sig, clear_preset_var2, true}}) {
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SigSpec q_sig = out_sig;
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if (neg) {
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q_sig = module->addWire(NEW_ID, out_sig.as_wire());
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