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Revisions (#4)

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* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <[email protected]>
This commit is contained in:
Tony Min
2024-07-08 10:57:16 -04:00
committed by GitHub
co-authored by tony
parent 6fe0e00050
commit d41688f7d7
44 changed files with 435 additions and 1118 deletions
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tests/arch/microchip/reduce.ys
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@@ -16,7 +16,7 @@
read_verilog reduce.v
synth_microchip -top reduce -abc9 -family polarfire -noiopad
synth_microchip -top reduce -family polarfire -noiopad
select -assert-count 1 t:XOR8
select -assert-none t:XOR8 %% t:* %D