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first round fixes

This commit is contained in:
Stan Lee 2026-01-20 21:45:13 -08:00
parent 29061d3051
commit d2e8f9b8a8
1 changed files with 1 additions and 6 deletions
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7
passes/silimate/reg_rename.cc
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@ -25,11 +25,6 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct RegWires {
std::vector<std::pair<Wire*, int>> oldWires;
int origRegWidth;
};
struct RegRenamePass : public Pass { struct RegRenamePass : public Pass {
RegRenamePass() : Pass("reg_rename", "renames register output wires to the correct register name and creates new wires for multi-bit registers for correct VCD register annotations.") { } RegRenamePass() : Pass("reg_rename", "renames register output wires to the correct register name and creates new wires for multi-bit registers for correct VCD register annotations.") { }
void help() override void help() override
@ -58,7 +53,7 @@ struct RegRenamePass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
// Populate data strucutre with register widths from VCD file // Populate data structure with register widths from VCD file
dict<std::string, int> vcd_reg_widths; dict<std::string, int> vcd_reg_widths;
if (!vcd_filename.empty()) { if (!vcd_filename.empty()) {
log("Reading VCD file: %s\n", vcd_filename.c_str()); log("Reading VCD file: %s\n", vcd_filename.c_str());