Merge pull request #5489 from rocallahan/fix-counter-reset

Fix `reset_auto_counter_id` to correctly detect `_NNN_` patterns

backends/verilog/verilog_backend.cc

@@ -116,21 +116,21 @@ void reset_auto_counter_id(RTLIL::IdString id, bool may_rename)
 	if (*it == '$' && may_rename && !norename)
 		auto_name_map[id] = auto_name_counter++;
 
-	if (*it != '\\' || *it != '_' || (it + 1) == it_end)
+	if (*it != '\\' || (it + 1) == it_end || *(it + 1) != '_' || (it + 2) == it_end)
 		return;
 
+	std::string s;
 	it += 2;
-	auto start = it;
 	while (it != it_end) {
 		char ch = *it;
 		if (ch == '_' && (it + 1) == it_end)
-			continue;
+			break;
 		if (ch < '0' || ch > '9')
 			return;
+		s.push_back(ch);
+		++it;
 	}
 
-	std::string s;
-	std::copy(start, it_end, std::back_inserter(s));
 	int num = atoi(s.c_str());
 	if (num >= auto_name_offset)
 		auto_name_offset = num + 1;

tests/verilog/.gitignore

@@ -1,6 +1,7 @@
 /const_arst.v
 /const_sr.v
 /doubleslash.v
+/reset_auto_counter.v
 /roundtrip_proc_1.v
 /roundtrip_proc_2.v
 /assign_to_reg.v

tests/verilog/reset_auto_counter.ys

@@ -0,0 +1,17 @@
+read_verilog -sv <<EOT
+module arithmetic (
+    input  logic [7:0] _0_,
+    input  logic [7:0] _1_,
+    output logic [7:0] _2_,
+);
+  assign _2_ = _0_ + _1_;
+
+endmodule : arithmetic
+EOT
+
+hierarchy
+techmap
+write_verilog reset_auto_counter.v
+! ! grep -qE '_0+0_' reset_auto_counter.v
+! ! grep -qE '_0+1_' reset_auto_counter.v
+! ! grep -qE '_0+2_' reset_auto_counter.v