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Renamed RTLIL::{Module,Cell}::connections to connections_

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This commit is contained in:
Clifford Wolf
2014-07-26 11:58:03 +02:00
parent 665759fcee
commit cc4f10883b
62 changed files with 1234 additions and 1213 deletions
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passes/techmap/iopadmap.cc
+4 -4
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@@ -177,9 +177,9 @@ struct IopadmapPass : public Pass {
for (int i = 0; i < wire->width; i++)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
if (!portname2.empty())
cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
if (!nameparam.empty())
@@ -190,9 +190,9 @@ struct IopadmapPass : public Pass {
else
{
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
if (!portname2.empty())
cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire);
cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire);
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty())