luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 14:17:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

Renamed RTLIL::{Module,Cell}::connections to connections_

Browse Source
This commit is contained in:
Clifford Wolf
2014-07-26 11:58:03 +02:00
parent 665759fcee
commit cc4f10883b
62 changed files with 1234 additions and 1213 deletions
Download Patch File Download Diff File Expand all files Collapse all files
passes/techmap/dfflibmap.cc
+2 -2
View File
@@ -398,7 +398,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
{
auto cell_type = cell->type;
auto cell_name = cell->name;
auto cell_connections = cell->connections;
auto cell_connections = cell->connections_;
module->remove(cell);
cell_mapping &cm = cell_mappings[cell_type];
@@ -418,7 +418,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
} else
if (port.second != 0)
log_abort();
new_cell->connections["\\" + port.first] = sig;
new_cell->connections_["\\" + port.first] = sig;
}
stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;