Add test

2026-08-22 06:07:26 +02:00 · 2019-08-07 16:29:38 -07:00
parent ea8ac8fd74
commit cc331cf70d
1 changed files with 10 additions and 1 deletions
@@ -1,6 +1,5 @@
 read_verilog test_arith.v
 synth_ice40
-techmap -map ../cells_sim.v
 rename test gate

 read_verilog test_arith.v
@@ -8,3 +7,13 @@ rename test gold

 miter -equiv -flatten -make_outputs gold gate miter
 sat -verify -prove trigger 0 -show-ports miter
+
+delete A:whitebox # Necessary since whiteboxes cannot
+                  # be overwritten...
+synth_ice40 -top gate
+
+read_verilog test_arith.v
+rename test gold
+
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 -show-ports miter