luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
Code Issues Packages Projects Releases Wiki Activity

log: convert all to sinks

Browse Source
This commit is contained in:
Miodrag Milanovic
2026-08-14 11:55:46 +02:00
parent bd5c524dc6
commit cbbd8c0dfd
14 changed files with 253 additions and 158 deletions
Download Patch File Download Diff File Expand all files Collapse all files
frontends/ast/simplify.cc
+12 -6
View File
@@ -2791,8 +2791,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
auto buf = children[0]->clone();
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
if (buf->type != AST_CONSTANT) {
// for (auto f : log_files)
// dumpAst(f, "verilog-ast> ");
// for (auto &s : log_sinks) {
// auto f = s->file_handle();
// if (f)
// dumpAst(f, "verilog-ast> ");
input_error("Condition for generate if is not constant!\n");
}
if (buf->asBool() != 0) {
@@ -2828,8 +2830,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
auto buf = children[0]->clone();
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
if (buf->type != AST_CONSTANT) {
// for (auto f : log_files)
// dumpAst(f, "verilog-ast> ");
// for (auto &s : log_sinks) {
// auto f = s->file_handle();
// if (f)
// dumpAst(f, "verilog-ast> ");
input_error("Condition for generate case is not constant!\n");
}
@@ -2862,8 +2866,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
buf->set_in_param_flag(true);
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
if (buf->type != AST_CONSTANT) {
// for (auto f : log_files)
// dumpAst(f, "verilog-ast> ");
// for (auto &s : log_sinks) {
// auto f = s->file_handle();
// if (f)
// dumpAst(f, "verilog-ast> ");
input_error("Expression in generate case is not constant!\n");
}