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Eddie Hung
2019-09-09 22:06:23 -07:00
parent 1fc50a03fc
commit cba63fe72b
1 changed files with 1 additions and 0 deletions
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passes/pmgen/xilinx_dsp.cc
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@@ -192,6 +192,7 @@ void pack_xilinx_simd(Module *module, const std::vector<Cell*> &selected_cells)
SigSpec Y = lane->getPort("\\Y");
A.extend_u0(24, lane->getParam("\\A_SIGNED").as_bool());
B.extend_u0(24, lane->getParam("\\B_SIGNED").as_bool());
C.append(A);
AB.append(B);
if (GetSize(Y) < 25)
Y.append(module->addWire(NEW_ID, 25-GetSize(Y)));