mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-08-29 01:24:25 +02:00
intel_alm: enable M10K initialisation
This commit is contained in:
@@ -2,6 +2,8 @@
|
||||
|
||||
module \$__MISTRAL_M10K (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
|
||||
parameter INIT = 0;
|
||||
|
||||
parameter CFG_ABITS = 10;
|
||||
parameter CFG_DBITS = 10;
|
||||
|
||||
@@ -11,6 +13,6 @@ input [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN, B1EN;
|
||||
output reg [CFG_DBITS-1:0] B1DATA;
|
||||
|
||||
MISTRAL_M10K #(.CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(!A1EN), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN));
|
||||
MISTRAL_M10K #(.INIT(INIT), .CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(!A1EN), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN));
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user