luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

rtlil: set Module* on inner-process AttrObjects at construction

This commit is contained in:
Emil J. Tywoniak 2026-06-05 14:29:40 +02:00
parent f1edb571f2
commit ca632e82c4
4 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
frontends/ast/genrtlil.cc
View File

@ -689,6 +689,7 @@ struct AST_INTERNAL::ProcessGenerator
ast->detectSignWidth(width_hint, sign_hint); ast->detectSignWidth(width_hint, sign_hint);
RTLIL::SwitchRule *sw = new RTLIL::SwitchRule; RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
sw->module = current_module;
set_src_attr(sw, ast); set_src_attr(sw, ast);
sw->signal = ast->children[0]->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap()); sw->signal = ast->children[0]->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap());
current_case->switches.push_back(sw); current_case->switches.push_back(sw);
@ -723,6 +724,7 @@ struct AST_INTERNAL::ProcessGenerator
RTLIL::CaseRule *backup_case = current_case; RTLIL::CaseRule *backup_case = current_case;
current_case = new RTLIL::CaseRule; current_case = new RTLIL::CaseRule;
current_case->module = current_module;
pool<RTLIL::SigBit> backup_assigned_bits = std::move(current_case_assigned_bits); pool<RTLIL::SigBit> backup_assigned_bits = std::move(current_case_assigned_bits);
current_case_assigned_bits.clear(); current_case_assigned_bits.clear();
set_src_attr(current_case, child.get()); set_src_attr(current_case, child.get());
@ -759,12 +761,14 @@ struct AST_INTERNAL::ProcessGenerator
last_generated_case->compare.clear(); last_generated_case->compare.clear();
#else #else
default_case = new RTLIL::CaseRule; default_case = new RTLIL::CaseRule;
default_case->module = current_module;
addChunkActions(default_case->actions, this_case_eq_ltemp, SigSpec(State::Sx, GetSize(this_case_eq_rvalue))); addChunkActions(default_case->actions, this_case_eq_ltemp, SigSpec(State::Sx, GetSize(this_case_eq_rvalue)));
sw->cases.push_back(default_case); sw->cases.push_back(default_case);
#endif #endif
} else { } else {
if (default_case == nullptr) { if (default_case == nullptr) {
default_case = new RTLIL::CaseRule; default_case = new RTLIL::CaseRule;
default_case->module = current_module;
addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue); addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
} }
sw->cases.push_back(default_case); sw->cases.push_back(default_case);

2
frontends/rtlil/rtlil_frontend.cc
View File

@ -838,6 +838,7 @@ struct RTLILFrontendWorker {
void parse_switch() void parse_switch()
{ {
RTLIL::SwitchRule *rule = new RTLIL::SwitchRule; RTLIL::SwitchRule *rule = new RTLIL::SwitchRule;
rule->module = current_module;
rule->signal = parse_sigspec(); rule->signal = parse_sigspec();
rule->absorb_attrs(std::move(attrbuf)); rule->absorb_attrs(std::move(attrbuf));
switch_stack.back()->push_back(rule); switch_stack.back()->push_back(rule);
@ -856,6 +857,7 @@ struct RTLILFrontendWorker {
expect_keyword("case"); expect_keyword("case");
RTLIL::CaseRule *case_rule = new RTLIL::CaseRule; RTLIL::CaseRule *case_rule = new RTLIL::CaseRule;
case_rule->module = current_module;
case_rule->absorb_attrs(std::move(attrbuf)); case_rule->absorb_attrs(std::move(attrbuf));
rule->cases.push_back(case_rule); rule->cases.push_back(case_rule);
switch_stack.push_back(&case_rule->switches); switch_stack.push_back(&case_rule->switches);

4
frontends/verific/verific.cc
View File

@ -1259,6 +1259,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
current_case = &proc->root_case; current_case = &proc->root_case;
RTLIL::SwitchRule *sw = new RTLIL::SwitchRule; RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
sw->module = module;
sw->signal = sig_select; sw->signal = sig_select;
current_case->switches.push_back(sw); current_case->switches.push_back(sw);
@ -1294,6 +1295,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
for (int32_t i = right; i<left; i++) { for (int32_t i = right; i<left; i++) {
RTLIL::CaseRule *cs = new RTLIL::CaseRule; RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->module = module;
cs->compare.push_back(RTLIL::Const(i,width)); cs->compare.push_back(RTLIL::Const(i,width));
cs->actions.push_back(action); cs->actions.push_back(action);
sw->cases.push_back(cs); sw->cases.push_back(cs);
@ -1301,12 +1303,14 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
} }
RTLIL::CaseRule *cs = new RTLIL::CaseRule; RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->module = module;
cs->compare.push_back(sel_left); cs->compare.push_back(sel_left);
cs->actions.push_back(action); cs->actions.push_back(action);
sw->cases.push_back(cs); sw->cases.push_back(cs);
} }
} }
RTLIL::CaseRule *cs_default = new RTLIL::CaseRule; RTLIL::CaseRule *cs_default = new RTLIL::CaseRule;
cs_default->module = module;
cs_default->actions.push_back(SigSig(sig_out_val, sig_data_default)); cs_default->actions.push_back(SigSig(sig_out_val, sig_data_default));
sw->cases.push_back(cs_default); sw->cases.push_back(cs_default);

3
passes/proc/proc_rom.cc
View File

@ -196,15 +196,18 @@ struct RomWorker
if (abits == GetSize(sw->signal)) { if (abits == GetSize(sw->signal)) {
sw->signal = SigSpec(); sw->signal = SigSpec();
RTLIL::CaseRule *cs = new RTLIL::CaseRule; RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->module = module;
cs->actions.push_back(SigSig(lhs, rdata)); cs->actions.push_back(SigSig(lhs, rdata));
sw->cases.push_back(cs); sw->cases.push_back(cs);
} else { } else {
sw->signal = sw->signal.extract_end(abits); sw->signal = sw->signal.extract_end(abits);
RTLIL::CaseRule *cs = new RTLIL::CaseRule; RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->module = module;
cs->compare.push_back(Const(State::S0, GetSize(sw->signal))); cs->compare.push_back(Const(State::S0, GetSize(sw->signal)));
cs->actions.push_back(SigSig(lhs, rdata)); cs->actions.push_back(SigSig(lhs, rdata));
sw->cases.push_back(cs); sw->cases.push_back(cs);
RTLIL::CaseRule *cs2 = new RTLIL::CaseRule; RTLIL::CaseRule *cs2 = new RTLIL::CaseRule;
cs2->module = module;
cs2->actions.push_back(SigSig(lhs, default_val)); cs2->actions.push_back(SigSig(lhs, default_val));
sw->cases.push_back(cs2); sw->cases.push_back(cs2);
} }