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Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup

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kernel: share a single CellTypes within a pass
This commit is contained in:
Eddie Hung
2020-04-01 14:17:45 -07:00
committed by GitHub
parent 4ae7f3a8ed 1d93d1e59f
commit c90324662c
4 changed files with 50 additions and 31 deletions
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passes/opt/opt_expr.cc
+3 -3
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@@ -31,9 +31,8 @@ PRIVATE_NAMESPACE_BEGIN
bool did_something;
void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
{
CellTypes ct(design);
SigMap sigmap(module);
SigPool driven_signals;
SigPool used_signals;
@@ -1803,13 +1802,14 @@ struct OptExprPass : public Pass {
}
extra_args(args, argidx, design);
CellTypes ct(design);
for (auto module : design->selected_modules())
{
log("Optimizing module %s.\n", log_id(module));
if (undriven) {
did_something = false;
replace_undriven(design, module);
replace_undriven(module, ct);
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
}