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Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup
kernel: share a single CellTypes within a pass
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+3
-10
@@ -380,22 +380,15 @@ struct ModWalker
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}
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}
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ModWalker() : design(NULL), module(NULL)
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ModWalker(RTLIL::Design *design) : design(design), module(NULL)
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{
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ct.setup(design);
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}
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ModWalker(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL)
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void setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)
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{
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setup(design, module, filter_ct);
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}
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void setup(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL)
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{
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this->design = design;
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this->module = module;
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ct.clear();
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ct.setup(design);
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sigmap.set(module);
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signal_drivers.clear();
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