mirror of https://github.com/YosysHQ/yosys.git
Merge 68df0be7d2 into 05805e8b93
This commit is contained in:
nella
GitHub
commit
c875f3223c
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@ -0,0 +1,79 @@
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#ifndef BITSIM_H
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#define BITSIM_H
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#include "kernel/modtools.h"
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YOSYS_NAMESPACE_BEGIN
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struct BitSim {
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Module *module;
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SigMap &sigmap;
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ModWalker &modwalker;
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dict<SigBit, uint64_t> sim_vals;
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uint64_t rng_state;
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BitSim(Module *m, SigMap &sm, ModWalker &mw)
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: module(m), sigmap(sm), modwalker(mw), rng_state(1337) {}
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uint64_t xorshift64() {
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rng_state ^= rng_state << 13;
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rng_state ^= rng_state >> 7;
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rng_state ^= rng_state << 17;
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return rng_state;
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}
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uint64_t eval_bit(SigBit b) {
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SigBit mapped = sigmap(b);
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if (mapped == State::S0) return 0ULL;
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if (mapped == State::S1) return ~0ULL;
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if (mapped == State::Sx || mapped == State::Sz) return 0ULL;
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auto it = sim_vals.find(mapped);
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if (it != sim_vals.end()) return it->second;
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sim_vals[mapped] = 0;
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uint64_t res = 0;
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if (!modwalker.has_drivers(mapped)) {
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res = xorshift64();
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} else {
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auto &drivers = modwalker.signal_drivers[mapped];
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if (drivers.empty()) {
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res = xorshift64();
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} else {
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auto driver = *drivers.begin();
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Cell *cell = driver.cell;
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if (cell->is_builtin_ff()) {
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res = xorshift64();
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} else if (cell->type == ID($_AND_)) {
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res = eval_bit(cell->getPort(ID::A)[0]) & eval_bit(cell->getPort(ID::B)[0]);
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} else if (cell->type == ID($_OR_)) {
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res = eval_bit(cell->getPort(ID::A)[0]) | eval_bit(cell->getPort(ID::B)[0]);
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} else if (cell->type == ID($_XOR_)) {
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res = eval_bit(cell->getPort(ID::A)[0]) ^ eval_bit(cell->getPort(ID::B)[0]);
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} else if (cell->type == ID($_NOT_)) {
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res = ~eval_bit(cell->getPort(ID::A)[0]);
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} else if (cell->type == ID($_MUX_)) {
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uint64_t s = eval_bit(cell->getPort(ID::S)[0]);
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uint64_t a = eval_bit(cell->getPort(ID::A)[0]);
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uint64_t b = eval_bit(cell->getPort(ID::B)[0]);
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res = (a & ~s) | (b & s);
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} else if (cell->type == ID($mux)) {
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uint64_t s = eval_bit(cell->getPort(ID::S)[0]);
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uint64_t a = eval_bit(cell->getPort(ID::A)[driver.offset]);
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uint64_t b = eval_bit(cell->getPort(ID::B)[driver.offset]);
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res = (a & ~s) | (b & s);
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} else {
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res = xorshift64();
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}
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}
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}
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sim_vals[mapped] = res;
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return res;
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}
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};
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YOSYS_NAMESPACE_END
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#endif
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@ -26,6 +26,7 @@
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/ff.h"
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#include "kernel/bitsim.h"
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#include "kernel/pattern.h"
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#include "passes/techmap/simplemap.h"
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#include <stdio.h>
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@ -919,6 +920,386 @@ struct OptDffWorker
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return did_something;
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}
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struct EqBit {
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Cell *cell;
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int idx;
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SigBit q;
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};
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struct SigKey {
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enum Flag : uint16_t {
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InitOne = 1u << 0,
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InitX = 1u << 1,
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PolClk = 1u << 2,
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PolCe = 1u << 3,
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PolSrst = 1u << 4,
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PolArst = 1u << 5,
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PolAload = 1u << 6,
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PolClr = 1u << 7,
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PolSet = 1u << 8,
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CeOverSrst = 1u << 9,
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};
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SigBit clk, ce, srst, arst, aload, clr, set;
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IdString cell_type; // for SR
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uint16_t flags;
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bool operator==(const SigKey &o) const {
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return flags == o.flags && clk == o.clk && ce == o.ce && srst == o.srst && arst == o.arst
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&& aload == o.aload && clr == o.clr && set == o.set && cell_type == o.cell_type;
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}
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Hasher hash_into(Hasher h) const {
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h.eat(flags);
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h.eat(clk);
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h.eat(ce);
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h.eat(srst);
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h.eat(arst);
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h.eat(aload);
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h.eat(clr);
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h.eat(set);
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h.eat(cell_type);
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return h;
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}
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};
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bool is_def(State s) {
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return s == State::S0 || s == State::S1;
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}
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int sat_mux(QuickConeSat &qcsat, int s, int a, int b) {
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return qcsat.ez->OR(qcsat.ez->AND(s, a), qcsat.ez->AND(qcsat.ez->NOT(s), b));
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}
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int sat_const(QuickConeSat &qcsat, State v) {
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return v == State::S1 ? qcsat.ez->CONST_TRUE : qcsat.ez->CONST_FALSE;
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}
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std::vector<std::vector<int>> gather_initial_eq_classes(std::vector<EqBit> &bits, dict<Cell *, FfData> &ff_for_cell)
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{
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std::vector<SigKey> keys;
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// Collect FF bits eligible for merging
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for (auto cell : module->selected_cells()) {
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if (!cell->is_builtin_ff())
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continue;
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FfData ff(&initvals, cell);
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if (!ff.has_clk && !ff.has_gclk)
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continue;
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ff_for_cell.emplace(cell, ff);
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for (int i = 0; i < ff.width; i++) {
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// X value
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if (ff.has_srst && !is_def(ff.val_srst[i])) continue;
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if (ff.has_arst && !is_def(ff.val_arst[i])) continue;
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// Missing anchor
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bool def_init = is_def(ff.val_init[i]);
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if (!def_init && !ff.has_srst && !ff.has_arst)
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continue;
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SigKey k = {};
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// Flags
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if (def_init && ff.val_init[i] == State::S1)
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k.flags |= SigKey::InitOne;
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else if (!def_init)
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k.flags |= SigKey::InitX;
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if (ff.has_clk) {
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k.clk = ff.sig_clk;
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if (ff.pol_clk) k.flags |= SigKey::PolClk;
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}
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if (ff.has_ce) {
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k.ce = ff.sig_ce;
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if (ff.pol_ce) k.flags |= SigKey::PolCe;
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}
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if (ff.has_srst) {
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k.srst = ff.sig_srst;
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if (ff.pol_srst) k.flags |= SigKey::PolSrst;
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if (ff.ce_over_srst) k.flags |= SigKey::CeOverSrst;
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}
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if (ff.has_arst) {
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k.arst = ff.sig_arst;
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if (ff.pol_arst) k.flags |= SigKey::PolArst;
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}
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if (ff.has_aload) {
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k.aload = ff.sig_aload;
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if (ff.pol_aload) k.flags |= SigKey::PolAload;
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}
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if (ff.has_sr) {
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k.clr = ff.sig_clr[i];
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k.set = ff.sig_set[i];
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k.cell_type = cell->type;
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if (ff.pol_clr) k.flags |= SigKey::PolClr;
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if (ff.pol_set) k.flags |= SigKey::PolSet;
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}
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bits.push_back({cell, i, ff.sig_q[i]});
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keys.push_back(k);
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}
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}
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dict<SigKey, std::vector<int>> buckets;
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for (int i = 0; i < GetSize(bits); i++)
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buckets[keys[i]].push_back(i);
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std::vector<std::vector<int>> classes;
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for (auto &kv : buckets)
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if (GetSize(kv.second) >= 2)
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classes.push_back(std::move(kv.second));
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return classes;
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}
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std::vector<std::vector<int>> filter_classes_sim(
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const std::vector<std::vector<int>> &classes,
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const std::vector<EqBit> &bits,
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const dict<Cell *, FfData> &ff_for_cell,
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ModWalker &modwalker
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) {
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BitSim sim(module, sigmap, modwalker);
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// Assume same class
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for (auto &cls : classes) {
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uint64_t class_q_val = sim.xorshift64();
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for (int idx : cls) {
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sim.sim_vals[sigmap(bits[idx].q)] = class_q_val;
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}
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}
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std::vector<std::vector<int>> refined_classes;
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for (auto &cls : classes) {
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dict<uint64_t, std::vector<int>> sim_buckets;
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for (int idx : cls) {
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const EqBit &eb = bits[idx];
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const FfData &ff = ff_for_cell.at(eb.cell);
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uint64_t n_val = sim.eval_bit(ff.sig_d[eb.idx]);
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if (ff.has_aload) {
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uint64_t al = sim.eval_bit(ff.sig_aload);
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if (!ff.pol_aload) al = ~al;
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uint64_t ad = sim.eval_bit(ff.sig_ad[eb.idx]);
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n_val = (n_val & ~al) | (ad & al);
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}
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if (ff.has_arst) {
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uint64_t ar = sim.eval_bit(ff.sig_arst);
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if (!ff.pol_arst) ar = ~ar;
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uint64_t ar_val = (ff.val_arst[eb.idx] == State::S1) ? ~0ULL : 0ULL;
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n_val = (n_val & ~ar) | (ar_val & ar);
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}
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if (ff.has_sr) {
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uint64_t clr = sim.eval_bit(ff.sig_clr[eb.idx]);
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if (!ff.pol_clr) clr = ~clr;
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uint64_t set = sim.eval_bit(ff.sig_set[eb.idx]);
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if (!ff.pol_set) set = ~set;
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n_val = ~clr & (set | n_val);
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}
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if (ff.has_srst) {
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uint64_t srst = sim.eval_bit(ff.sig_srst);
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if (!ff.pol_srst) srst = ~srst;
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uint64_t srst_val = (ff.val_srst[eb.idx] == State::S1) ? ~0ULL : 0ULL;
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n_val = (n_val & ~srst) | (srst_val & srst);
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}
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sim_buckets[n_val].push_back(idx);
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}
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for (auto &kv : sim_buckets)
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if (GetSize(kv.second) >= 2)
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refined_classes.push_back(std::move(kv.second));
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}
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return refined_classes;
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}
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std::vector<std::vector<int>> filter_classes_sat(
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std::vector<std::vector<int>> classes,
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const std::vector<EqBit> &bits,
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const dict<Cell *, FfData> &ff_for_cell,
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ModWalker &modwalker
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) {
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QuickConeSat qcsat(modwalker);
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std::vector<int> q_lit(bits.size(), -1);
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std::vector<int> n_lit(bits.size(), -1);
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// Per candidate SAT for its next state, model difference
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for (auto &cls : classes) {
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for (int idx : cls) {
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const EqBit &eb = bits[idx];
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const FfData &ff = ff_for_cell.at(eb.cell);
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q_lit[idx] = qcsat.importSigBit(eb.q);
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int n = qcsat.importSigBit(ff.sig_d[eb.idx]);
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if (ff.has_aload) {
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int al = qcsat.importSigBit(ff.sig_aload);
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if (!ff.pol_aload) al = qcsat.ez->NOT(al);
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n = sat_mux(qcsat, al, qcsat.importSigBit(ff.sig_ad[eb.idx]), n);
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}
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if (ff.has_arst) {
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int ar = qcsat.importSigBit(ff.sig_arst);
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if (!ff.pol_arst) ar = qcsat.ez->NOT(ar);
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n = sat_mux(qcsat, ar, sat_const(qcsat, ff.val_arst[eb.idx]), n);
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}
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if (ff.has_sr) {
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int clr = qcsat.importSigBit(ff.sig_clr[eb.idx]);
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if (!ff.pol_clr) clr = qcsat.ez->NOT(clr);
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int set = qcsat.importSigBit(ff.sig_set[eb.idx]);
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if (!ff.pol_set) set = qcsat.ez->NOT(set);
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n = qcsat.ez->AND(qcsat.ez->NOT(clr), qcsat.ez->OR(set, n));
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}
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if (ff.has_srst) {
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int srst = qcsat.importSigBit(ff.sig_srst);
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if (!ff.pol_srst) srst = qcsat.ez->NOT(srst);
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n = sat_mux(qcsat, srst, sat_const(qcsat, ff.val_srst[eb.idx]), n);
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}
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n_lit[idx] = n;
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}
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}
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qcsat.prepare();
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std::vector<int> worklist;
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std::vector<bool> in_worklist(GetSize(classes), true);
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|
||||
for (int i = 0; i < GetSize(classes); i++)
|
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worklist.push_back(i);
|
||||
|
||||
while (!worklist.empty()) {
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int cls_idx = worklist.back();
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worklist.pop_back();
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in_worklist[cls_idx] = false;
|
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auto &cls = classes[cls_idx];
|
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if (GetSize(cls) < 2) continue;
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|
||||
std::vector<int> assumptions;
|
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for (auto &c : classes) {
|
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if (GetSize(c) < 2) continue;
|
||||
int rep = c[0];
|
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for (int k = 1; k < GetSize(c); k++)
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assumptions.push_back(qcsat.ez->IFF(q_lit[rep], q_lit[c[k]]));
|
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}
|
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|
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// Split at counterexamples
|
||||
int rep = cls[0];
|
||||
for (int i = 1; i < GetSize(cls); i++) {
|
||||
// Trivially equivalent
|
||||
if (n_lit[rep] == n_lit[cls[i]])
|
||||
continue;
|
||||
|
||||
int query = qcsat.ez->NOT(qcsat.ez->IFF(n_lit[rep], n_lit[cls[i]]));
|
||||
std::vector<int> modelExprs;
|
||||
for (int b : cls)
|
||||
modelExprs.push_back(n_lit[b]);
|
||||
|
||||
std::vector<bool> modelVals;
|
||||
assumptions.push_back(query);
|
||||
|
||||
if (qcsat.ez->solve(modelExprs, modelVals, assumptions)) {
|
||||
// SAT -> partition entire class
|
||||
std::vector<int> sub0;
|
||||
std::vector<int> sub1;
|
||||
|
||||
for (size_t b_idx = 0; b_idx < cls.size(); b_idx++) {
|
||||
if (modelVals[b_idx])
|
||||
sub1.push_back(cls[b_idx]);
|
||||
else
|
||||
sub0.push_back(cls[b_idx]);
|
||||
}
|
||||
|
||||
classes[cls_idx] = std::move(sub0);
|
||||
classes.push_back(std::move(sub1));
|
||||
in_worklist.push_back(false);
|
||||
|
||||
// Partition was split -> the induction hypo weakened
|
||||
for (int j = 0; j < GetSize(classes); j++) {
|
||||
if (GetSize(classes[j]) >= 2 && !in_worklist[j]) {
|
||||
worklist.push_back(j);
|
||||
in_worklist[j] = true;
|
||||
}
|
||||
}
|
||||
|
||||
break; // Process new splits
|
||||
}
|
||||
|
||||
assumptions.pop_back(); // Remove query for the next pairwise check if UNSAT
|
||||
}
|
||||
}
|
||||
|
||||
return classes;
|
||||
}
|
||||
|
||||
bool apply_eq_merges(const std::vector<std::vector<int>> &classes, const std::vector<EqBit> &bits, dict<Cell *, FfData> &ff_for_cell)
|
||||
{
|
||||
bool any_change = false;
|
||||
dict<Cell *, std::set<int>> remove_bits;
|
||||
|
||||
// Drive every non-rep Q from its class rep, drop merged bits from their FFs
|
||||
for (auto &cls : classes) {
|
||||
if (GetSize(cls) < 2)
|
||||
continue;
|
||||
SigBit rep_q = bits[cls[0]].q;
|
||||
any_change = true;
|
||||
for (int k = 1; k < GetSize(cls); k++) {
|
||||
const EqBit &eb = bits[cls[k]];
|
||||
initvals.remove_init(eb.q);
|
||||
module->connect(eb.q, rep_q);
|
||||
remove_bits[eb.cell].insert(eb.idx);
|
||||
}
|
||||
}
|
||||
|
||||
for (auto &kv : remove_bits) {
|
||||
Cell *cell = kv.first;
|
||||
const std::set<int> &drop = kv.second;
|
||||
FfData &ff = ff_for_cell.at(cell);
|
||||
std::vector<int> keep;
|
||||
|
||||
for (int i = 0; i < ff.width; i++)
|
||||
if (!drop.count(i))
|
||||
keep.push_back(i);
|
||||
|
||||
if (keep.empty()) {
|
||||
module->remove(cell);
|
||||
} else {
|
||||
FfData new_ff = ff.slice(keep);
|
||||
new_ff.cell = cell;
|
||||
new_ff.emit();
|
||||
}
|
||||
}
|
||||
|
||||
return any_change;
|
||||
}
|
||||
|
||||
bool run_eqbits()
|
||||
{
|
||||
if (!opt.sat)
|
||||
return false;
|
||||
|
||||
std::vector<EqBit> bits;
|
||||
dict<Cell *, FfData> ff_for_cell;
|
||||
|
||||
std::vector<std::vector<int>> classes = gather_initial_eq_classes(bits, ff_for_cell);
|
||||
if (classes.empty())
|
||||
return false;
|
||||
|
||||
ModWalker modwalker(module->design, module);
|
||||
|
||||
// Simulation prepass
|
||||
classes = filter_classes_sim(classes, bits, ff_for_cell, modwalker);
|
||||
if (classes.empty())
|
||||
return false;
|
||||
|
||||
// SAT prove
|
||||
classes = filter_classes_sat(std::move(classes), bits, ff_for_cell, modwalker);
|
||||
if (classes.empty())
|
||||
return false;
|
||||
|
||||
return apply_eq_merges(classes, bits, ff_for_cell);
|
||||
}
|
||||
};
|
||||
|
||||
struct OptDffPass : public Pass {
|
||||
|
|
@ -987,6 +1368,8 @@ struct OptDffPass : public Pass {
|
|||
did_something = true;
|
||||
if (worker.run_constbits())
|
||||
did_something = true;
|
||||
if (worker.run_eqbits())
|
||||
did_something = true;
|
||||
}
|
||||
|
||||
if (did_something)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,56 @@
|
|||
# small test case
|
||||
design -reset
|
||||
read_verilog -sv opt_dff_eqbits_small.sv
|
||||
hierarchy -top test_case
|
||||
techmap
|
||||
opt_dff -sat
|
||||
synth
|
||||
opt_dff -sat
|
||||
opt_clean -purge
|
||||
|
||||
select -assert-count 2 t:$_SDFF_PN0_
|
||||
|
||||
# equivalence
|
||||
design -reset
|
||||
read_verilog -sv opt_dff_eqbits_small.sv
|
||||
hierarchy -top test_case
|
||||
prep
|
||||
design -save gold
|
||||
|
||||
opt_dff -sat
|
||||
design -save gate
|
||||
|
||||
design -copy-from gold -as gold test_case
|
||||
design -copy-from gate -as gate test_case
|
||||
equiv_make gold gate equiv
|
||||
equiv_induct equiv
|
||||
equiv_status -assert
|
||||
|
||||
|
||||
# large test case
|
||||
design -reset
|
||||
read_verilog -sv opt_dff_eqbits_large.sv
|
||||
hierarchy -top test_case
|
||||
techmap
|
||||
opt_dff -sat
|
||||
synth
|
||||
opt_dff -sat
|
||||
opt_clean -purge
|
||||
|
||||
select -assert-count 6 t:$_SDFFE_PN0P_
|
||||
|
||||
# equivalence
|
||||
design -reset
|
||||
read_verilog -sv opt_dff_eqbits_large.sv
|
||||
hierarchy -top test_case
|
||||
prep
|
||||
design -save gold
|
||||
|
||||
opt_dff -sat
|
||||
design -save gate
|
||||
|
||||
design -copy-from gold -as gold test_case
|
||||
design -copy-from gate -as gate test_case
|
||||
equiv_make gold gate equiv
|
||||
equiv_induct equiv
|
||||
equiv_status -assert
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
module test_case (
|
||||
input wire clk,
|
||||
input wire rst_n,
|
||||
input wire [3:0] chan_0_data,
|
||||
input wire chan_0_vld,
|
||||
input wire chan_1_rdy,
|
||||
output wire chan_0_rdy,
|
||||
output wire [207:0] chan_1_data,
|
||||
output wire chan_1_vld,
|
||||
output wire idle
|
||||
);
|
||||
wire [12:0] state_init[0:15];
|
||||
assign state_init[0] = 13'h0000;
|
||||
assign state_init[1] = 13'h0000;
|
||||
assign state_init[2] = 13'h0000;
|
||||
assign state_init[3] = 13'h0000;
|
||||
assign state_init[4] = 13'h0000;
|
||||
assign state_init[5] = 13'h0000;
|
||||
assign state_init[6] = 13'h0000;
|
||||
assign state_init[7] = 13'h0000;
|
||||
assign state_init[8] = 13'h0000;
|
||||
assign state_init[9] = 13'h0000;
|
||||
assign state_init[10] = 13'h0000;
|
||||
assign state_init[11] = 13'h0000;
|
||||
assign state_init[12] = 13'h0000;
|
||||
assign state_init[13] = 13'h0000;
|
||||
assign state_init[14] = 13'h0000;
|
||||
assign state_init[15] = 13'h0000;
|
||||
|
||||
wire [12:0] ch1_init[0:15];
|
||||
assign ch1_init[0] = 13'h0000;
|
||||
assign ch1_init[1] = 13'h0000;
|
||||
assign ch1_init[2] = 13'h0000;
|
||||
assign ch1_init[3] = 13'h0000;
|
||||
assign ch1_init[4] = 13'h0000;
|
||||
assign ch1_init[5] = 13'h0000;
|
||||
assign ch1_init[6] = 13'h0000;
|
||||
assign ch1_init[7] = 13'h0000;
|
||||
assign ch1_init[8] = 13'h0000;
|
||||
assign ch1_init[9] = 13'h0000;
|
||||
assign ch1_init[10] = 13'h0000;
|
||||
assign ch1_init[11] = 13'h0000;
|
||||
assign ch1_init[12] = 13'h0000;
|
||||
assign ch1_init[13] = 13'h0000;
|
||||
assign ch1_init[14] = 13'h0000;
|
||||
assign ch1_init[15] = 13'h0000;
|
||||
|
||||
wire [12:0] mask_1fff[0:15];
|
||||
assign mask_1fff[0] = 13'h1fff;
|
||||
assign mask_1fff[1] = 13'h1fff;
|
||||
assign mask_1fff[2] = 13'h1fff;
|
||||
assign mask_1fff[3] = 13'h1fff;
|
||||
assign mask_1fff[4] = 13'h1fff;
|
||||
assign mask_1fff[5] = 13'h1fff;
|
||||
assign mask_1fff[6] = 13'h1fff;
|
||||
assign mask_1fff[7] = 13'h1fff;
|
||||
assign mask_1fff[8] = 13'h1fff;
|
||||
assign mask_1fff[9] = 13'h1fff;
|
||||
assign mask_1fff[10] = 13'h1fff;
|
||||
assign mask_1fff[11] = 13'h1fff;
|
||||
assign mask_1fff[12] = 13'h1fff;
|
||||
assign mask_1fff[13] = 13'h1fff;
|
||||
assign mask_1fff[14] = 13'h1fff;
|
||||
assign mask_1fff[15] = 13'h1fff;
|
||||
|
||||
reg [12:0] state_array[0:15];
|
||||
reg [3:0] ch0_in_buf;
|
||||
reg ch0_in_buf_vld;
|
||||
reg [12:0] ch1_out_buf[0:15];
|
||||
reg ch1_out_buf_vld;
|
||||
reg stg1_vld;
|
||||
|
||||
wire ch1_not_vld;
|
||||
wire [3:0] ch0_sel_data;
|
||||
wire ch0_is_vld;
|
||||
wire ch1_vld_we;
|
||||
wire ch1_data_we;
|
||||
wire stg0_vld_out;
|
||||
wire ch0_buf_ready;
|
||||
wire ch0_pipe_stall;
|
||||
wire [1:0] sel_concat;
|
||||
wire ch0_buf_data_we;
|
||||
wire ch0_buf_vld_rst;
|
||||
wire stg0_idle;
|
||||
wire stg1_idle;
|
||||
wire ch0_is_inactive;
|
||||
wire ch1_is_inactive;
|
||||
wire [12:0] next_state_val[0:15];
|
||||
wire state_we;
|
||||
wire ch0_buf_vld_we;
|
||||
wire stg1_vld_we;
|
||||
wire pipe_idle;
|
||||
|
||||
assign ch1_not_vld = ~ch1_out_buf_vld;
|
||||
assign ch0_sel_data = ch0_in_buf_vld ? ch0_in_buf : chan_0_data;
|
||||
assign ch0_is_vld = chan_0_vld | ch0_in_buf_vld;
|
||||
assign ch1_vld_we = chan_1_rdy | ch1_not_vld;
|
||||
assign ch1_data_we = ch0_is_vld & ch1_vld_we;
|
||||
assign stg0_vld_out = ch0_is_vld & ch1_data_we;
|
||||
assign ch0_buf_ready = ~ch0_in_buf_vld;
|
||||
assign ch0_pipe_stall = ~stg0_vld_out;
|
||||
assign sel_concat = {ch0_is_vld & ch0_sel_data[0], ch0_is_vld & ~ch0_sel_data[0]};
|
||||
assign ch0_buf_data_we = chan_0_vld & ch0_buf_ready & ch0_pipe_stall;
|
||||
assign ch0_buf_vld_rst = ch0_in_buf_vld & stg0_vld_out;
|
||||
assign stg0_idle = ~ch0_is_vld;
|
||||
assign stg1_idle = ~stg1_vld;
|
||||
assign ch0_is_inactive = ~(chan_0_vld & ch0_buf_ready);
|
||||
assign ch1_is_inactive = ~(ch1_out_buf_vld & chan_1_rdy);
|
||||
|
||||
assign next_state_val[0] = state_array[0] & {13{sel_concat[0]}} | mask_1fff[0] & {13{sel_concat[1]}};
|
||||
assign next_state_val[1] = state_array[1] & {13{sel_concat[0]}} | mask_1fff[1] & {13{sel_concat[1]}};
|
||||
assign next_state_val[2] = state_array[2] & {13{sel_concat[0]}} | mask_1fff[2] & {13{sel_concat[1]}};
|
||||
assign next_state_val[3] = state_array[3] & {13{sel_concat[0]}} | mask_1fff[3] & {13{sel_concat[1]}};
|
||||
assign next_state_val[4] = state_array[4] & {13{sel_concat[0]}} | mask_1fff[4] & {13{sel_concat[1]}};
|
||||
assign next_state_val[5] = state_array[5] & {13{sel_concat[0]}} | mask_1fff[5] & {13{sel_concat[1]}};
|
||||
assign next_state_val[6] = state_array[6] & {13{sel_concat[0]}} | mask_1fff[6] & {13{sel_concat[1]}};
|
||||
assign next_state_val[7] = state_array[7] & {13{sel_concat[0]}} | mask_1fff[7] & {13{sel_concat[1]}};
|
||||
assign next_state_val[8] = state_array[8] & {13{sel_concat[0]}} | mask_1fff[8] & {13{sel_concat[1]}};
|
||||
assign next_state_val[9] = state_array[9] & {13{sel_concat[0]}} | mask_1fff[9] & {13{sel_concat[1]}};
|
||||
assign next_state_val[10] = state_array[10] & {13{sel_concat[0]}} | mask_1fff[10] & {13{sel_concat[1]}};
|
||||
assign next_state_val[11] = state_array[11] & {13{sel_concat[0]}} | mask_1fff[11] & {13{sel_concat[1]}};
|
||||
assign next_state_val[12] = state_array[12] & {13{sel_concat[0]}} | mask_1fff[12] & {13{sel_concat[1]}};
|
||||
assign next_state_val[13] = state_array[13] & {13{sel_concat[0]}} | mask_1fff[13] & {13{sel_concat[1]}};
|
||||
assign next_state_val[14] = state_array[14] & {13{sel_concat[0]}} | mask_1fff[14] & {13{sel_concat[1]}};
|
||||
assign next_state_val[15] = state_array[15] & {13{sel_concat[0]}} | mask_1fff[15] & {13{sel_concat[1]}};
|
||||
|
||||
assign state_we = stg0_vld_out & ch0_sel_data[0] | stg0_vld_out & ~ch0_sel_data[0];
|
||||
assign ch0_buf_vld_we = ch0_buf_data_we | ch0_buf_vld_rst;
|
||||
assign stg1_vld_we = stg0_vld_out | stg1_vld;
|
||||
assign pipe_idle = stg0_idle & stg1_idle & ch0_is_inactive & ch1_is_inactive;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
state_array[0] <= state_init[0];
|
||||
state_array[1] <= state_init[1];
|
||||
state_array[2] <= state_init[2];
|
||||
state_array[3] <= state_init[3];
|
||||
state_array[4] <= state_init[4];
|
||||
state_array[5] <= state_init[5];
|
||||
state_array[6] <= state_init[6];
|
||||
state_array[7] <= state_init[7];
|
||||
state_array[8] <= state_init[8];
|
||||
state_array[9] <= state_init[9];
|
||||
state_array[10] <= state_init[10];
|
||||
state_array[11] <= state_init[11];
|
||||
state_array[12] <= state_init[12];
|
||||
state_array[13] <= state_init[13];
|
||||
state_array[14] <= state_init[14];
|
||||
state_array[15] <= state_init[15];
|
||||
ch0_in_buf <= 4'h0;
|
||||
ch0_in_buf_vld <= 1'h0;
|
||||
ch1_out_buf[0] <= ch1_init[0];
|
||||
ch1_out_buf[1] <= ch1_init[1];
|
||||
ch1_out_buf[2] <= ch1_init[2];
|
||||
ch1_out_buf[3] <= ch1_init[3];
|
||||
ch1_out_buf[4] <= ch1_init[4];
|
||||
ch1_out_buf[5] <= ch1_init[5];
|
||||
ch1_out_buf[6] <= ch1_init[6];
|
||||
ch1_out_buf[7] <= ch1_init[7];
|
||||
ch1_out_buf[8] <= ch1_init[8];
|
||||
ch1_out_buf[9] <= ch1_init[9];
|
||||
ch1_out_buf[10] <= ch1_init[10];
|
||||
ch1_out_buf[11] <= ch1_init[11];
|
||||
ch1_out_buf[12] <= ch1_init[12];
|
||||
ch1_out_buf[13] <= ch1_init[13];
|
||||
ch1_out_buf[14] <= ch1_init[14];
|
||||
ch1_out_buf[15] <= ch1_init[15];
|
||||
ch1_out_buf_vld <= 1'h0;
|
||||
stg1_vld <= 1'h0;
|
||||
end else begin
|
||||
state_array[0] <= state_we ? next_state_val[0] : state_array[0];
|
||||
state_array[1] <= state_we ? next_state_val[1] : state_array[1];
|
||||
state_array[2] <= state_we ? next_state_val[2] : state_array[2];
|
||||
state_array[3] <= state_we ? next_state_val[3] : state_array[3];
|
||||
state_array[4] <= state_we ? next_state_val[4] : state_array[4];
|
||||
state_array[5] <= state_we ? next_state_val[5] : state_array[5];
|
||||
state_array[6] <= state_we ? next_state_val[6] : state_array[6];
|
||||
state_array[7] <= state_we ? next_state_val[7] : state_array[7];
|
||||
state_array[8] <= state_we ? next_state_val[8] : state_array[8];
|
||||
state_array[9] <= state_we ? next_state_val[9] : state_array[9];
|
||||
state_array[10] <= state_we ? next_state_val[10] : state_array[10];
|
||||
state_array[11] <= state_we ? next_state_val[11] : state_array[11];
|
||||
state_array[12] <= state_we ? next_state_val[12] : state_array[12];
|
||||
state_array[13] <= state_we ? next_state_val[13] : state_array[13];
|
||||
state_array[14] <= state_we ? next_state_val[14] : state_array[14];
|
||||
state_array[15] <= state_we ? next_state_val[15] : state_array[15];
|
||||
ch0_in_buf <= ch0_buf_data_we ? chan_0_data : ch0_in_buf;
|
||||
ch0_in_buf_vld <= ch0_buf_vld_we ? ch0_buf_ready : ch0_in_buf_vld;
|
||||
ch1_out_buf[0] <= ch1_data_we ? state_array[0] : ch1_out_buf[0];
|
||||
ch1_out_buf[1] <= ch1_data_we ? state_array[1] : ch1_out_buf[1];
|
||||
ch1_out_buf[2] <= ch1_data_we ? state_array[2] : ch1_out_buf[2];
|
||||
ch1_out_buf[3] <= ch1_data_we ? state_array[3] : ch1_out_buf[3];
|
||||
ch1_out_buf[4] <= ch1_data_we ? state_array[4] : ch1_out_buf[4];
|
||||
ch1_out_buf[5] <= ch1_data_we ? state_array[5] : ch1_out_buf[5];
|
||||
ch1_out_buf[6] <= ch1_data_we ? state_array[6] : ch1_out_buf[6];
|
||||
ch1_out_buf[7] <= ch1_data_we ? state_array[7] : ch1_out_buf[7];
|
||||
ch1_out_buf[8] <= ch1_data_we ? state_array[8] : ch1_out_buf[8];
|
||||
ch1_out_buf[9] <= ch1_data_we ? state_array[9] : ch1_out_buf[9];
|
||||
ch1_out_buf[10] <= ch1_data_we ? state_array[10] : ch1_out_buf[10];
|
||||
ch1_out_buf[11] <= ch1_data_we ? state_array[11] : ch1_out_buf[11];
|
||||
ch1_out_buf[12] <= ch1_data_we ? state_array[12] : ch1_out_buf[12];
|
||||
ch1_out_buf[13] <= ch1_data_we ? state_array[13] : ch1_out_buf[13];
|
||||
ch1_out_buf[14] <= ch1_data_we ? state_array[14] : ch1_out_buf[14];
|
||||
ch1_out_buf[15] <= ch1_data_we ? state_array[15] : ch1_out_buf[15];
|
||||
ch1_out_buf_vld <= ch1_vld_we ? ch0_is_vld : ch1_out_buf_vld;
|
||||
stg1_vld <= stg1_vld_we ? stg0_vld_out : stg1_vld;
|
||||
end
|
||||
end
|
||||
|
||||
assign chan_0_rdy = ch0_buf_ready;
|
||||
assign chan_1_data = {
|
||||
ch1_out_buf[15],
|
||||
ch1_out_buf[14],
|
||||
ch1_out_buf[13],
|
||||
ch1_out_buf[12],
|
||||
ch1_out_buf[11],
|
||||
ch1_out_buf[10],
|
||||
ch1_out_buf[9],
|
||||
ch1_out_buf[8],
|
||||
ch1_out_buf[7],
|
||||
ch1_out_buf[6],
|
||||
ch1_out_buf[5],
|
||||
ch1_out_buf[4],
|
||||
ch1_out_buf[3],
|
||||
ch1_out_buf[2],
|
||||
ch1_out_buf[1],
|
||||
ch1_out_buf[0]
|
||||
};
|
||||
assign chan_1_vld = ch1_out_buf_vld;
|
||||
assign idle = pipe_idle;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
module test_case (
|
||||
input wire clk,
|
||||
input wire rst_n,
|
||||
input wire in_val,
|
||||
output wire out_a,
|
||||
output wire out_b,
|
||||
output wire out_c,
|
||||
output wire out_d
|
||||
);
|
||||
reg a, b, c, d;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
a <= 1'b0;
|
||||
b <= 1'b0;
|
||||
c <= 1'b0;
|
||||
d <= 1'b0;
|
||||
end else begin
|
||||
a <= c & in_val;
|
||||
b <= d & in_val;
|
||||
c <= b | in_val;
|
||||
d <= a | in_val;
|
||||
end
|
||||
end
|
||||
|
||||
assign out_a = a;
|
||||
assign out_b = b;
|
||||
assign out_c = c;
|
||||
assign out_d = d;
|
||||
endmodule
|
||||
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Reference in New Issue