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fabulous: add `-extra-mlibmap` option, remove legacy `-noregfile` option 

- this allows to map to any memories
- to map legacy register files, use: `-extra-plib regfile.v -extra-mlibmap ram_regfile.txt -extra-map regfile_map.v`

Signed-off-by: Leo Moser <leomoser99@gmail.com>
This commit is contained in:
Leo Moser 2026-06-24 14:15:38 +02:00
parent 6c82468031
commit c73fd4f70b
3 changed files with 17 additions and 103 deletions
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46
techlibs/fabulous/ram_regfile.txt
View File

@ -1,46 +0,0 @@
# Yosys doesn't support configurable sync/async ports.
# So we define three RAMs for 2xasync, 1xsync 1xasync and 2xsync
ram distributed $__REGFILE_AA_ {
abits 5;
width 4;
cost 6;
port sw "W" {
clock posedge "CLK";
}
port ar "A" {
}
port ar "B" {
}
}
ram distributed $__REGFILE_SA_ {
abits 5;
width 4;
cost 5;
port sw "W" {
clock posedge "CLK";
wrtrans all old;
}
port sr "A" {
clock posedge "CLK";
}
port ar "B" {
}
}
ram distributed $__REGFILE_SS_ {
abits 5;
width 4;
cost 4;
port sw "W" {
clock posedge "CLK";
wrtrans all old;
}
port sr "A" {
clock posedge "CLK";
}
port sr "B" {
clock posedge "CLK";
}
}

42
techlibs/fabulous/regfile_map.v
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@ -1,42 +0,0 @@
(* techmap_celltype = "$__REGFILE_[AS][AS]_" *)
module \$__REGFILE_XX_ (...);
parameter _TECHMAP_CELLTYPE_ = "";
localparam [0:0] B_SYNC = _TECHMAP_CELLTYPE_[15:8] == "S";
localparam [0:0] A_SYNC = _TECHMAP_CELLTYPE_[23:16] == "S";
localparam WIDTH = 4;
localparam ABITS = 5;
input [WIDTH-1:0] PORT_W_WR_DATA;
input [ABITS-1:0] PORT_W_ADDR;
input PORT_W_WR_EN;
output [WIDTH-1:0] PORT_A_RD_DATA;
input [ABITS-1:0] PORT_A_ADDR;
output [WIDTH-1:0] PORT_B_RD_DATA;
input [ABITS-1:0] PORT_B_ADDR;
// Unused - we have a shared clock - but keep techmap happy
input PORT_W_CLK;
input PORT_A_CLK;
input PORT_B_CLK;
input CLK_CLK;
RegFile_32x4 #(
.AD_reg(A_SYNC),
.BD_reg(B_SYNC)
) _TECHMAP_REPLACE_ (
.D0(PORT_W_WR_DATA[0]), .D1(PORT_W_WR_DATA[1]), .D2(PORT_W_WR_DATA[2]), .D3(PORT_W_WR_DATA[3]),
.W_ADR0(PORT_W_ADDR[0]), .W_ADR1(PORT_W_ADDR[1]), .W_ADR2(PORT_W_ADDR[2]), .W_ADR3(PORT_W_ADDR[3]), .W_ADR4(PORT_W_ADDR[4]),
.W_en(PORT_W_WR_EN),
.AD0(PORT_A_RD_DATA[0]), .AD1(PORT_A_RD_DATA[1]), .AD2(PORT_A_RD_DATA[2]), .AD3(PORT_A_RD_DATA[3]),
.A_ADR0(PORT_A_ADDR[0]), .A_ADR1(PORT_A_ADDR[1]), .A_ADR2(PORT_A_ADDR[2]), .A_ADR3(PORT_A_ADDR[3]), .A_ADR4(PORT_A_ADDR[4]),
.BD0(PORT_B_RD_DATA[0]), .BD1(PORT_B_RD_DATA[1]), .BD2(PORT_B_RD_DATA[2]), .BD3(PORT_B_RD_DATA[3]),
.B_ADR0(PORT_B_ADDR[0]), .B_ADR1(PORT_B_ADDR[1]), .B_ADR2(PORT_B_ADDR[2]), .B_ADR3(PORT_B_ADDR[3]), .B_ADR4(PORT_B_ADDR[4]),
.CLK(CLK_CLK)
);
endmodule

32
techlibs/fabulous/synth_fabulous.cc
View File

@ -66,6 +66,10 @@ struct SynthPass : public ScriptPass
log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n"); log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n");
log(" times).\n"); log(" times).\n");
log("\n"); log("\n");
log(" -extra-mlibmap <memory_map.txt>\n");
log(" use the provided library convert memory into hardware supported memory (can be specified\n");
log(" multiple times).\n");
log("\n");
log(" -nofsm\n"); log(" -nofsm\n");
log(" do not run FSM optimization\n"); log(" do not run FSM optimization\n");
log("\n"); log("\n");
@ -76,9 +80,6 @@ struct SynthPass : public ScriptPass
log(" -carry <none|ha>\n"); log(" -carry <none|ha>\n");
log(" carry mapping style (none, half-adders, ...) default=none\n"); log(" carry mapping style (none, half-adders, ...) default=none\n");
log("\n"); log("\n");
log(" -noregfile\n");
log(" do not map register files\n");
log("\n");
log(" -iopad\n"); log(" -iopad\n");
log(" enable automatic insertion of IO buffers (otherwise a wrapper\n"); log(" enable automatic insertion of IO buffers (otherwise a wrapper\n");
log(" with manually inserted and constrained IO should be used.)\n"); log(" with manually inserted and constrained IO should be used.)\n");
@ -109,10 +110,10 @@ struct SynthPass : public ScriptPass
} }
string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode; string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode;
std::vector<string> extra_plib, extra_map; std::vector<string> extra_plib, extra_map, extra_mlibmap;
std::vector<std::pair<string, string>> extra_ffs; std::vector<std::pair<string, string>> extra_ffs;
bool autotop, noalumacc, nofsm, noshare, noregfile, iopad, flatten; bool autotop, noalumacc, nofsm, noshare, iopad, flatten;
int lut; int lut;
void clear_flags() override void clear_flags() override
@ -183,6 +184,10 @@ struct SynthPass : public ScriptPass
extra_map.push_back(args[++argidx]); extra_map.push_back(args[++argidx]);
continue; continue;
} }
if (args[argidx] == "-extra-mlibmap" && argidx+1 < args.size()) {
extra_mlibmap.push_back(args[++argidx]);
continue;
}
if (args[argidx] == "-nofsm") { if (args[argidx] == "-nofsm") {
nofsm = true; nofsm = true;
continue; continue;
@ -203,10 +208,6 @@ struct SynthPass : public ScriptPass
memory_opts += " -no-rw-check"; memory_opts += " -no-rw-check";
continue; continue;
} }
if (args[argidx] == "-noregfile") {
noregfile = true;
continue;
}
if (args[argidx] == "-iopad") { if (args[argidx] == "-iopad") {
iopad = true; iopad = true;
continue; continue;
@ -294,12 +295,13 @@ struct SynthPass : public ScriptPass
run("opt_clean"); run("opt_clean");
} }
if (check_label("map_ram", "(unless -noregfile)")) { if (check_label("map_memory")) {
// RegFile extraction if (help_mode) {
if (!noregfile) { run("memory_libmap -lib <memory_map.txt>", "(for each -extra-mlibmap)");
run("memory_libmap -lib +/fabulous/ram_regfile.txt"); } else
run("techmap -map +/fabulous/regfile_map.v"); for (auto lib : extra_mlibmap) {
} run("memory_libmap -lib " + lib);
}
} }
if (check_label("map_ffram")) { if (check_label("map_ffram")) {