mirror of https://github.com/YosysHQ/yosys.git
Implement constbit gather.
This commit is contained in:
nella
parent
0cf045b3bd
commit
c6371c2da8
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@ -248,6 +248,9 @@ struct OptDffWorker
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OptDffWorker(const OptDffOptions &opt, Module *mod)
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: opt(opt), module(mod), sigmap(mod), initvals(&sigmap, mod)
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{
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sat_effort = (int64_t)module->design->scratchpad_get_int("opt_dff.sat_effort", 1000000) * 1000;
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sat_effort_left = sat_effort;
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// Gathering two kinds of information here for every sigmapped SigBit:
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// - bitusers: how many users it has (muxes will only be merged into FFs if the FF is the only user)
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// - bit2mux: the mux cell and bit index that drives it, if any
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@ -970,16 +973,46 @@ struct OptDffWorker
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return val;
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}
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// One FF bit whose constness needs SAT proofs; each target is a non-const input (D and/or AD)
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// that must be shown eq to val
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struct ConstTarget {
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SigBit sig;
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int lit = -1;
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bool proven = false;
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};
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struct ConstObligation {
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Cell *cell;
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int idx;
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State val;
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SigBit q;
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int q_lit = -1;
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bool dropped = false;
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std::vector<ConstTarget> targets;
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};
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bool run_constbits()
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{
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// Find FFs that are provably constant
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ModWalker modwalker(module->design, module);
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QuickConeSat qcsat(modwalker);
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std::vector<RTLIL::Cell*> cells_to_remove;
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std::vector<FfData> ffs_to_emit;
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dict<Cell *, pool<int>> const_bits;
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bool did_something = false;
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auto commit_const = [&](Cell *cell, int i, SigBit q, State val) {
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log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n",
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val == State::S1 ? 1 : 0, i, cell, cell->type.unescape(), module);
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initvals.remove_init(q);
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module->connect(q, val);
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const_bits[cell].insert(i);
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did_something = true;
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};
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// Fold constant D/AD inputs into the tested value directly bits whose remaining inputs are
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// wires become SAT proof obligations
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std::vector<ConstObligation> obligations;
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for (auto cell : module->selected_cells()) {
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if (!cell->is_builtin_ff())
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continue;
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@ -992,58 +1025,181 @@ struct OptDffWorker
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if (val == State::Sm)
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continue;
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// Check Synchronous input D
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if (ff.has_clk || ff.has_gclk) {
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if (!ff.sig_d[i].wire) {
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// D is already a constant
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val = combine_const(val, ff.sig_d[i].data);
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if (val == State::Sm) continue;
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} else if (opt.sat) {
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// Try SAT proof for non-constant D wires
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if (!prove_const_with_sat(qcsat, modwalker, ff.sig_q[i], ff.sig_d[i], val))
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continue;
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} else {
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continue;
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}
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// Fold all const inputs first, so the SAT targets are checked against the final const
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if ((ff.has_clk || ff.has_gclk) && !ff.sig_d[i].wire) {
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val = combine_const(val, ff.sig_d[i].data);
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if (val == State::Sm) continue;
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}
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if (ff.has_aload && !ff.sig_ad[i].wire) {
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val = combine_const(val, ff.sig_ad[i].data);
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if (val == State::Sm) continue;
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}
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// Check Async Load input AD
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if (ff.has_aload) {
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if (!ff.sig_ad[i].wire) {
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val = combine_const(val, ff.sig_ad[i].data);
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if (val == State::Sm) continue;
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} else if (opt.sat) {
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if (!prove_const_with_sat(qcsat, modwalker, ff.sig_q[i], ff.sig_ad[i], val))
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continue;
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} else {
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continue;
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ConstObligation ob;
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ob.cell = cell;
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ob.idx = i;
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ob.val = val;
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ob.q = ff.sig_q[i];
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bool feasible = true;
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auto add_target = [&](SigBit sig) {
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if (!opt.sat || (val != State::S0 && val != State::S1) ||
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!modwalker.has_drivers(sig)) {
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feasible = false;
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return;
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}
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ConstTarget t;
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t.sig = sig;
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ob.targets.push_back(t);
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};
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if ((ff.has_clk || ff.has_gclk) && ff.sig_d[i].wire)
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add_target(ff.sig_d[i]);
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if (feasible && ff.has_aload && ff.sig_ad[i].wire)
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add_target(ff.sig_ad[i]);
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if (!feasible)
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continue;
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if (ob.targets.empty()) {
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commit_const(cell, i, ff.sig_q[i], val);
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continue;
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}
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obligations.push_back(ob);
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}
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}
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log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n",
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val ? 1 : 0, i, cell, cell->type.unescape(), module);
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int64_t screen_cap = 0;
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if (sat_effort > 0 && !obligations.empty()) {
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// Screening cap, scaled down when the budget cannot afford a full-price screening round
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int64_t num_queries = 0;
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for (auto &ob : obligations)
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num_queries += GetSize(ob.targets);
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screen_cap = max((int64_t)20000, min((int64_t)200000, sat_effort / (4 * num_queries)));
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}
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// Replace the Q output with the constant value
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initvals.remove_init(ff.sig_q[i]);
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module->connect(ff.sig_q[i], val);
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removed_sigbits.insert(i);
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for (int batch_begin = 0; batch_begin < GetSize(obligations) && !sat_budget_spent(); ) {
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QuickConeSat qcsat(modwalker);
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int64_t cells_charged = 0;
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int batch_end = batch_begin;
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while (batch_end < GetSize(obligations) && !sat_budget_spent()) {
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if (batch_end > batch_begin && GetSize(qcsat.imported_cells) >= sat_batch_cells)
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break;
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auto &ob = obligations[batch_end];
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ob.q_lit = qcsat.importSigBit(ob.q);
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for (auto &t : ob.targets)
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t.lit = qcsat.importSigBit(t.sig);
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qcsat.prepare();
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charge_import(qcsat, cells_charged);
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batch_end++;
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}
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// Reconstruct FF with constant bits removed
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if (!removed_sigbits.empty()) {
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std::vector<int> keep_bits;
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for (int i = 0; i < ff.width; i++)
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if (!removed_sigbits.count(i))
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keep_bits.push_back(i);
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int64_t cap = screen_cap;
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bool out_of_budget = false;
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if (keep_bits.empty()) {
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cells_to_remove.push_back(cell);
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} else {
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ff = ff.slice(keep_bits);
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ff.cell = cell;
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ffs_to_emit.push_back(ff);
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while (!out_of_budget) {
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bool all_resolved = true;
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for (int obi = batch_begin; obi < batch_end; obi++) {
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auto &ob = obligations[obi];
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if (ob.dropped)
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continue;
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for (auto &t : ob.targets) {
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if (t.proven || ob.dropped)
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continue;
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if (sat_budget_spent()) {
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out_of_budget = true;
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break;
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}
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std::vector<int> modelExprs;
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std::vector<ConstObligation *> model_obs;
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for (int obi2 = batch_begin; obi2 < batch_end; obi2++) {
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auto &ob2 = obligations[obi2];
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if (ob2.dropped)
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continue;
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for (auto &t2 : ob2.targets)
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if (!t2.proven) {
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modelExprs.push_back(t2.lit);
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modelExprs.push_back(ob2.q_lit);
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model_obs.push_back(&ob2);
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}
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}
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// Prove that the next value equals the constant in every state where Q already holds it
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int vlit = qcsat.ez->value(ob.val == State::S1);
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std::vector<int> assumptions;
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assumptions.push_back(qcsat.ez->IFF(ob.q_lit, vlit));
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assumptions.push_back(qcsat.ez->NOT(qcsat.ez->IFF(t.lit, vlit)));
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std::vector<bool> modelVals;
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int res = solve_budgeted(qcsat, cap, modelExprs, modelVals, assumptions);
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if (res < 0) {
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all_resolved = false;
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continue;
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}
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if (res == 0) {
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t.proven = true;
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continue;
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}
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// Counterexample: this bit is not constant
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// Any other pending bit whose Q holds its constant while its next value differs is
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// disproven by the same state
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for (int k = 0; k < GetSize(model_obs); k++) {
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ConstObligation *ob2 = model_obs[k];
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if (ob2->dropped)
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continue;
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bool want = (ob2->val == State::S1);
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bool t_val = modelVals[2*k];
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bool q_val = modelVals[2*k + 1];
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if (q_val == want && t_val != want)
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ob2->dropped = true;
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}
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ob.dropped = true;
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}
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if (out_of_budget)
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break;
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}
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did_something = true;
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if (out_of_budget || all_resolved)
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break;
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cap = 0;
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}
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batch_begin = batch_end;
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}
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for (auto &ob : obligations) {
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if (ob.dropped)
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continue;
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bool all_proven = true;
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for (auto &t : ob.targets)
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all_proven &= t.proven;
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if (all_proven)
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commit_const(ob.cell, ob.idx, ob.q, ob.val);
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}
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// Reconstruct FF with constant bits removed
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std::vector<RTLIL::Cell*> cells_to_remove;
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std::vector<FfData> ffs_to_emit;
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for (auto &kv : const_bits) {
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Cell *cell = kv.first;
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FfData ff(&initvals, cell);
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std::vector<int> keep_bits;
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for (int i = 0; i < ff.width; i++)
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if (!kv.second.count(i))
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keep_bits.push_back(i);
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if (keep_bits.empty()) {
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cells_to_remove.push_back(cell);
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} else {
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ff = ff.slice(keep_bits);
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ff.cell = cell;
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ffs_to_emit.push_back(ff);
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}
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}
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