fmt: %t/$time support

backends/cxxrtl/cxxrtl.h

@@ -1330,7 +1330,10 @@ struct module {
 	virtual bool eval() = 0;
 	virtual bool commit() = 0;
 
+	unsigned int steps = 0;
+
 	size_t step() {
+		++steps;
 		size_t deltas = 0;
 		bool converged = false;
 		do {

backends/verilog/verilog_backend.cc

@@ -1797,6 +1797,12 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 					dump_sigspec(f, arg.sig);
 					f << ")";
 					break;
+				case VerilogFmtArg::TIME:
+					if (arg.realtime)
+						f << "$realtime";
+					else
+						f << "$time";
+					break;
 				default: log_abort();
 			}
 		}